diff --git a/Lib/mk20dx128.h b/Lib/mk20dx128.h
index e974a15..7ab6773 100644
--- a/Lib/mk20dx128.h
+++ b/Lib/mk20dx128.h
@@ -1085,6 +1085,7 @@ extern "C" {
 #define UART_S1_PF			(uint8_t)0x01			// Parity Error Flag
 #define UART0_S2                *(volatile uint8_t  *)0x4006A005 // UART Status Register 2
 #define UART_S2_RXINV			(uint8_t)0x10			// RX Line Inversion Enable
+#define UART_S2_MSBF			(uint8_t)0x20			// MSBF Format Enabled
 #define UART0_C3                *(volatile uint8_t  *)0x4006A006 // UART Control Register 3
 #define UART_S2_TXINV			(uint8_t)0x10			// TX Line Inversion Enable
 #define UART0_D                 *(volatile uint8_t  *)0x4006A007 // UART Data Register
diff --git a/Scan/MBC-55X/scan_loop.c b/Scan/MBC-55X/scan_loop.c
index d476bce..f0cf245 100644
--- a/Scan/MBC-55X/scan_loop.c
+++ b/Scan/MBC-55X/scan_loop.c
@@ -148,7 +148,7 @@ inline void scan_setup()
 	UART0_BDL = (uint8_t)baud;
 
 	// 8 bit, Even Parity, Idle Character bit after stop
-	UART0_C1 = ~UART_C1_M | UART_C1_PE | ~UART_C1_PT | UART_C1_ILT;
+	UART0_C1 = ~UART_C1_M | ~UART_C1_PE | UART_C1_PT | UART_C1_ILT;
 
 	// Number of bytes in FIFO before TX Interrupt
 	UART0_TWFIFO = 1;
@@ -163,15 +163,15 @@ inline void scan_setup()
 	//  0x2 - 8 dataword
 	UART0_PFIFO = ~UART_PFIFO_TXFE | /*TXFIFOSIZE*/ (0x0 << 4) | ~UART_PFIFO_RXFE | /*RXFIFOSIZE*/ (0x0);
 
-	// TX Disabled, RX Enabled, RX Interrupt Enabled
-	UART0_C2 = UART_C2_TE | UART_C2_RE | UART_C2_RIE;
-
-	// Reciever Inversion Disabled
-	UART0_S2 = ~UART_S2_RXINV;
+	// Reciever Inversion Disabled, LSBF
+	UART0_S2 = ~UART_S2_RXINV | UART_S2_MSBF;
 
 	// Transmit Inversion Disabled
 	UART0_C3 = ~UART_S2_TXINV;
 
+	// TX Disabled, RX Enabled, RX Interrupt Enabled
+	UART0_C2 = UART_C2_TE | UART_C2_RE | UART_C2_RIE;
+
 	// Add interrupt to the vector table
 	NVIC_ENABLE_IRQ( IRQ_UART0_STATUS );
 
@@ -185,6 +185,7 @@ inline void scan_setup()
 inline uint8_t scan_loop()
 {
 	UART0_D = 0x56;
+	UART0_D = 0x1C;
 	_delay_ms( 100 );
 	return 0;
 }