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@@ -29,9 +29,13 @@ |
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* SOFTWARE. |
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*/ |
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// Local Includes |
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#include "mk20dx.h" |
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// ----- Variables ----- |
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extern unsigned long _stext; |
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extern unsigned long _etext; |
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extern unsigned long _sdata; |
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@@ -39,321 +43,327 @@ extern unsigned long _edata; |
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extern unsigned long _sbss; |
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extern unsigned long _ebss; |
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extern unsigned long _estack; |
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extern int main (void); |
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void ResetHandler(void); |
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void __libc_init_array(void); |
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void fault_isr(void) |
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// ----- Function Declarations ----- |
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extern int main (); |
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void ResetHandler(); |
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// ----- Interrupts ----- |
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// NVIC - Default ISR |
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void fault_isr() |
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{ |
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while (1) { |
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while ( 1 ) |
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{ |
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// keep polling some communication while in fault |
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// mode, so we don't completely die. |
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if (SIM_SCGC4 & SIM_SCGC4_USBOTG) usb_isr(); |
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if (SIM_SCGC4 & SIM_SCGC4_UART0) uart0_status_isr(); |
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if (SIM_SCGC4 & SIM_SCGC4_UART1) uart1_status_isr(); |
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if (SIM_SCGC4 & SIM_SCGC4_UART2) uart2_status_isr(); |
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if ( SIM_SCGC4 & SIM_SCGC4_USBOTG ) usb_isr(); |
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if ( SIM_SCGC4 & SIM_SCGC4_UART0 ) uart0_status_isr(); |
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if ( SIM_SCGC4 & SIM_SCGC4_UART1 ) uart1_status_isr(); |
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if ( SIM_SCGC4 & SIM_SCGC4_UART2 ) uart2_status_isr(); |
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} |
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} |
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void unused_isr(void) |
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void unused_isr() |
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{ |
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fault_isr(); |
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} |
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// NVIC - SysTick ISR |
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extern volatile uint32_t systick_millis_count; |
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void systick_default_isr(void) |
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void systick_default_isr() |
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{ |
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systick_millis_count++; |
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} |
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void nmi_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void hard_fault_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void memmanage_fault_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void bus_fault_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void usage_fault_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void svcall_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void debugmonitor_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void pendablesrvreq_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void systick_isr(void) __attribute__ ((weak, alias("systick_default_isr"))); |
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void dma_ch0_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch1_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch2_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch3_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch4_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch5_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch6_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch7_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch8_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch9_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch10_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch11_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch12_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch13_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch14_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch15_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dma_error_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void mcm_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void flash_cmd_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void flash_error_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void low_voltage_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void wakeup_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void watchdog_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void i2c0_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void i2c1_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void i2c2_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void spi0_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void spi1_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void spi2_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void sdhc_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void can0_message_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void can0_bus_off_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void can0_error_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void can0_tx_warn_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void can0_rx_warn_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void can0_wakeup_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void i2s0_tx_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void i2s0_rx_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart0_lon_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart0_status_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart0_error_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart1_status_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart1_error_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart2_status_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart2_error_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart3_status_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart3_error_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart4_status_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart4_error_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart5_status_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void uart5_error_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void adc0_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void adc1_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void cmp0_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void cmp1_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void cmp2_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void ftm0_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void ftm1_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void ftm2_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void ftm3_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void cmt_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void rtc_alarm_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void rtc_seconds_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void pit0_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void pit1_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void pit2_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void pit3_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void pdb_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void usb_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void usb_charge_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dac0_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void dac1_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void tsi0_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void mcg_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void lptmr_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void porta_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void portb_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void portc_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void portd_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void porte_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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void software_isr(void) __attribute__ ((weak, alias("unused_isr"))); |
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// TODO: create AVR-stype ISR() macro, with default linkage to undefined handler |
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// |
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// NVIC - Default ISR/Vector Linking |
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void nmi_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void hard_fault_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void memmanage_fault_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void bus_fault_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void usage_fault_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void svcall_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void debugmonitor_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void pendablesrvreq_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void systick_isr() __attribute__ ((weak, alias("systick_default_isr"))); |
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void dma_ch0_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch1_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch2_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch3_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch4_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch5_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch6_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch7_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch8_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch9_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch10_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch11_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch12_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch13_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch14_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_ch15_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dma_error_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void mcm_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void flash_cmd_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void flash_error_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void low_voltage_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void wakeup_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void watchdog_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void i2c0_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void i2c1_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void i2c2_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void spi0_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void spi1_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void spi2_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void sdhc_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void can0_message_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void can0_bus_off_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void can0_error_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void can0_tx_warn_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void can0_rx_warn_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void can0_wakeup_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void i2s0_tx_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void i2s0_rx_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart0_lon_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart0_status_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart0_error_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart1_status_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart1_error_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart2_status_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart2_error_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart3_status_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart3_error_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart4_status_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart4_error_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart5_status_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void uart5_error_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void adc0_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void adc1_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void cmp0_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void cmp1_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void cmp2_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void ftm0_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void ftm1_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void ftm2_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void ftm3_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void cmt_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void rtc_alarm_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void rtc_seconds_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void pit0_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void pit1_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void pit2_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void pit3_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void pdb_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void usb_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void usb_charge_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dac0_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void dac1_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void tsi0_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void mcg_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void lptmr_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void porta_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void portb_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void portc_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void portd_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void porte_isr() __attribute__ ((weak, alias("unused_isr"))); |
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void software_isr() __attribute__ ((weak, alias("unused_isr"))); |
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// NVIC - Interrupt Vector Table |
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__attribute__ ((section(".vectors"), used)) |
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void (* const gVectors[])(void) = |
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void (* const gVectors[])() = |
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{ |
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(void (*)(void))((unsigned long)&_estack), // 0 ARM: Initial Stack Pointer |
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ResetHandler, // 1 ARM: Initial Program Counter |
|
|
|
nmi_isr, // 2 ARM: Non-maskable Interrupt (NMI) |
|
|
|
hard_fault_isr, // 3 ARM: Hard Fault |
|
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|
memmanage_fault_isr, // 4 ARM: MemManage Fault |
|
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|
bus_fault_isr, // 5 ARM: Bus Fault |
|
|
|
usage_fault_isr, // 6 ARM: Usage Fault |
|
|
|
fault_isr, // 7 -- |
|
|
|
fault_isr, // 8 -- |
|
|
|
fault_isr, // 9 -- |
|
|
|
fault_isr, // 10 -- |
|
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|
svcall_isr, // 11 ARM: Supervisor call (SVCall) |
|
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|
debugmonitor_isr, // 12 ARM: Debug Monitor |
|
|
|
fault_isr, // 13 -- |
|
|
|
pendablesrvreq_isr, // 14 ARM: Pendable req serv(PendableSrvReq) |
|
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|
systick_isr, // 15 ARM: System tick timer (SysTick) |
|
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|
(void (*)(void))((unsigned long)&_estack), // 0 ARM: Initial Stack Pointer |
|
|
|
ResetHandler, // 1 ARM: Initial Program Counter |
|
|
|
nmi_isr, // 2 ARM: Non-maskable Interrupt (NMI) |
|
|
|
hard_fault_isr, // 3 ARM: Hard Fault |
|
|
|
memmanage_fault_isr, // 4 ARM: MemManage Fault |
|
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bus_fault_isr, // 5 ARM: Bus Fault |
|
|
|
usage_fault_isr, // 6 ARM: Usage Fault |
|
|
|
fault_isr, // 7 -- |
|
|
|
fault_isr, // 8 -- |
|
|
|
fault_isr, // 9 -- |
|
|
|
fault_isr, // 10 -- |
|
|
|
svcall_isr, // 11 ARM: Supervisor call (SVCall) |
|
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|
debugmonitor_isr, // 12 ARM: Debug Monitor |
|
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|
fault_isr, // 13 -- |
|
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|
pendablesrvreq_isr, // 14 ARM: Pendable req serv(PendableSrvReq) |
|
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|
systick_isr, // 15 ARM: System tick timer (SysTick) |
|
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|
#if defined(_mk20dx128_) || defined(_mk20dx128vlf5_) |
|
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|
dma_ch0_isr, // 16 DMA channel 0 transfer complete |
|
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dma_ch1_isr, // 17 DMA channel 1 transfer complete |
|
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dma_ch2_isr, // 18 DMA channel 2 transfer complete |
|
|
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dma_ch3_isr, // 19 DMA channel 3 transfer complete |
|
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dma_error_isr, // 20 DMA error interrupt channel |
|
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unused_isr, // 21 DMA -- |
|
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flash_cmd_isr, // 22 Flash Memory Command complete |
|
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flash_error_isr, // 23 Flash Read collision |
|
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low_voltage_isr, // 24 Low-voltage detect/warning |
|
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wakeup_isr, // 25 Low Leakage Wakeup |
|
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watchdog_isr, // 26 Both EWM and WDOG interrupt |
|
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i2c0_isr, // 27 I2C0 |
|
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spi0_isr, // 28 SPI0 |
|
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|
i2s0_tx_isr, // 29 I2S0 Transmit |
|
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i2s0_rx_isr, // 30 I2S0 Receive |
|
|
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uart0_lon_isr, // 31 UART0 CEA709.1-B (LON) status |
|
|
|
uart0_status_isr, // 32 UART0 status |
|
|
|
uart0_error_isr, // 33 UART0 error |
|
|
|
uart1_status_isr, // 34 UART1 status |
|
|
|
uart1_error_isr, // 35 UART1 error |
|
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|
uart2_status_isr, // 36 UART2 status |
|
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uart2_error_isr, // 37 UART2 error |
|
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adc0_isr, // 38 ADC0 |
|
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cmp0_isr, // 39 CMP0 |
|
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cmp1_isr, // 40 CMP1 |
|
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ftm0_isr, // 41 FTM0 |
|
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|
ftm1_isr, // 42 FTM1 |
|
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cmt_isr, // 43 CMT |
|
|
|
rtc_alarm_isr, // 44 RTC Alarm interrupt |
|
|
|
rtc_seconds_isr, // 45 RTC Seconds interrupt |
|
|
|
pit0_isr, // 46 PIT Channel 0 |
|
|
|
pit1_isr, // 47 PIT Channel 1 |
|
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|
pit2_isr, // 48 PIT Channel 2 |
|
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|
pit3_isr, // 49 PIT Channel 3 |
|
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|
pdb_isr, // 50 PDB Programmable Delay Block |
|
|
|
usb_isr, // 51 USB OTG |
|
|
|
usb_charge_isr, // 52 USB Charger Detect |
|
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|
tsi0_isr, // 53 TSI0 |
|
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|
mcg_isr, // 54 MCG |
|
|
|
lptmr_isr, // 55 Low Power Timer |
|
|
|
porta_isr, // 56 Pin detect (Port A) |
|
|
|
portb_isr, // 57 Pin detect (Port B) |
|
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|
portc_isr, // 58 Pin detect (Port C) |
|
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|
portd_isr, // 59 Pin detect (Port D) |
|
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porte_isr, // 60 Pin detect (Port E) |
|
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software_isr, // 61 Software interrupt |
|
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dma_ch0_isr, // 16 DMA channel 0 transfer complete |
|
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|
dma_ch1_isr, // 17 DMA channel 1 transfer complete |
|
|
|
dma_ch2_isr, // 18 DMA channel 2 transfer complete |
|
|
|
dma_ch3_isr, // 19 DMA channel 3 transfer complete |
|
|
|
dma_error_isr, // 20 DMA error interrupt channel |
|
|
|
unused_isr, // 21 DMA -- |
|
|
|
flash_cmd_isr, // 22 Flash Memory Command complete |
|
|
|
flash_error_isr, // 23 Flash Read collision |
|
|
|
low_voltage_isr, // 24 Low-voltage detect/warning |
|
|
|
wakeup_isr, // 25 Low Leakage Wakeup |
|
|
|
watchdog_isr, // 26 Both EWM and WDOG interrupt |
|
|
|
i2c0_isr, // 27 I2C0 |
|
|
|
spi0_isr, // 28 SPI0 |
|
|
|
i2s0_tx_isr, // 29 I2S0 Transmit |
|
|
|
i2s0_rx_isr, // 30 I2S0 Receive |
|
|
|
uart0_lon_isr, // 31 UART0 CEA709.1-B (LON) status |
|
|
|
uart0_status_isr, // 32 UART0 status |
|
|
|
uart0_error_isr, // 33 UART0 error |
|
|
|
uart1_status_isr, // 34 UART1 status |
|
|
|
uart1_error_isr, // 35 UART1 error |
|
|
|
uart2_status_isr, // 36 UART2 status |
|
|
|
uart2_error_isr, // 37 UART2 error |
|
|
|
adc0_isr, // 38 ADC0 |
|
|
|
cmp0_isr, // 39 CMP0 |
|
|
|
cmp1_isr, // 40 CMP1 |
|
|
|
ftm0_isr, // 41 FTM0 |
|
|
|
ftm1_isr, // 42 FTM1 |
|
|
|
cmt_isr, // 43 CMT |
|
|
|
rtc_alarm_isr, // 44 RTC Alarm interrupt |
|
|
|
rtc_seconds_isr, // 45 RTC Seconds interrupt |
|
|
|
pit0_isr, // 46 PIT Channel 0 |
|
|
|
pit1_isr, // 47 PIT Channel 1 |
|
|
|
pit2_isr, // 48 PIT Channel 2 |
|
|
|
pit3_isr, // 49 PIT Channel 3 |
|
|
|
pdb_isr, // 50 PDB Programmable Delay Block |
|
|
|
usb_isr, // 51 USB OTG |
|
|
|
usb_charge_isr, // 52 USB Charger Detect |
|
|
|
tsi0_isr, // 53 TSI0 |
|
|
|
mcg_isr, // 54 MCG |
|
|
|
lptmr_isr, // 55 Low Power Timer |
|
|
|
porta_isr, // 56 Pin detect (Port A) |
|
|
|
portb_isr, // 57 Pin detect (Port B) |
|
|
|
portc_isr, // 58 Pin detect (Port C) |
|
|
|
portd_isr, // 59 Pin detect (Port D) |
|
|
|
porte_isr, // 60 Pin detect (Port E) |
|
|
|
software_isr, // 61 Software interrupt |
|
|
|
#elif defined(_mk20dx256_) |
|
|
|
dma_ch0_isr, // 16 DMA channel 0 transfer complete |
|
|
|
dma_ch1_isr, // 17 DMA channel 1 transfer complete |
|
|
|
dma_ch2_isr, // 18 DMA channel 2 transfer complete |
|
|
|
dma_ch3_isr, // 19 DMA channel 3 transfer complete |
|
|
|
dma_ch4_isr, // 20 DMA channel 4 transfer complete |
|
|
|
dma_ch5_isr, // 21 DMA channel 5 transfer complete |
|
|
|
dma_ch6_isr, // 22 DMA channel 6 transfer complete |
|
|
|
dma_ch7_isr, // 23 DMA channel 7 transfer complete |
|
|
|
dma_ch8_isr, // 24 DMA channel 8 transfer complete |
|
|
|
dma_ch9_isr, // 25 DMA channel 9 transfer complete |
|
|
|
dma_ch10_isr, // 26 DMA channel 10 transfer complete |
|
|
|
dma_ch11_isr, // 27 DMA channel 10 transfer complete |
|
|
|
dma_ch12_isr, // 28 DMA channel 10 transfer complete |
|
|
|
dma_ch13_isr, // 29 DMA channel 10 transfer complete |
|
|
|
dma_ch14_isr, // 30 DMA channel 10 transfer complete |
|
|
|
dma_ch15_isr, // 31 DMA channel 10 transfer complete |
|
|
|
dma_error_isr, // 32 DMA error interrupt channel |
|
|
|
unused_isr, // 33 -- |
|
|
|
flash_cmd_isr, // 34 Flash Memory Command complete |
|
|
|
flash_error_isr, // 35 Flash Read collision |
|
|
|
low_voltage_isr, // 36 Low-voltage detect/warning |
|
|
|
wakeup_isr, // 37 Low Leakage Wakeup |
|
|
|
watchdog_isr, // 38 Both EWM and WDOG interrupt |
|
|
|
unused_isr, // 39 -- |
|
|
|
i2c0_isr, // 40 I2C0 |
|
|
|
i2c1_isr, // 41 I2C1 |
|
|
|
spi0_isr, // 42 SPI0 |
|
|
|
spi1_isr, // 43 SPI1 |
|
|
|
unused_isr, // 44 -- |
|
|
|
can0_message_isr, // 45 CAN OR'ed Message buffer (0-15) |
|
|
|
can0_bus_off_isr, // 46 CAN Bus Off |
|
|
|
can0_error_isr, // 47 CAN Error |
|
|
|
can0_tx_warn_isr, // 48 CAN Transmit Warning |
|
|
|
can0_rx_warn_isr, // 49 CAN Receive Warning |
|
|
|
can0_wakeup_isr, // 50 CAN Wake Up |
|
|
|
i2s0_tx_isr, // 51 I2S0 Transmit |
|
|
|
i2s0_rx_isr, // 52 I2S0 Receive |
|
|
|
unused_isr, // 53 -- |
|
|
|
unused_isr, // 54 -- |
|
|
|
unused_isr, // 55 -- |
|
|
|
unused_isr, // 56 -- |
|
|
|
unused_isr, // 57 -- |
|
|
|
unused_isr, // 58 -- |
|
|
|
unused_isr, // 59 -- |
|
|
|
uart0_lon_isr, // 60 UART0 CEA709.1-B (LON) status |
|
|
|
uart0_status_isr, // 61 UART0 status |
|
|
|
uart0_error_isr, // 62 UART0 error |
|
|
|
uart1_status_isr, // 63 UART1 status |
|
|
|
uart1_error_isr, // 64 UART1 error |
|
|
|
uart2_status_isr, // 65 UART2 status |
|
|
|
uart2_error_isr, // 66 UART2 error |
|
|
|
unused_isr, // 67 -- |
|
|
|
unused_isr, // 68 -- |
|
|
|
unused_isr, // 69 -- |
|
|
|
unused_isr, // 70 -- |
|
|
|
unused_isr, // 71 -- |
|
|
|
unused_isr, // 72 -- |
|
|
|
adc0_isr, // 73 ADC0 |
|
|
|
adc1_isr, // 74 ADC1 |
|
|
|
cmp0_isr, // 75 CMP0 |
|
|
|
cmp1_isr, // 76 CMP1 |
|
|
|
cmp2_isr, // 77 CMP2 |
|
|
|
ftm0_isr, // 78 FTM0 |
|
|
|
ftm1_isr, // 79 FTM1 |
|
|
|
ftm2_isr, // 80 FTM2 |
|
|
|
cmt_isr, // 81 CMT |
|
|
|
rtc_alarm_isr, // 82 RTC Alarm interrupt |
|
|
|
rtc_seconds_isr, // 83 RTC Seconds interrupt |
|
|
|
pit0_isr, // 84 PIT Channel 0 |
|
|
|
pit1_isr, // 85 PIT Channel 1 |
|
|
|
pit2_isr, // 86 PIT Channel 2 |
|
|
|
pit3_isr, // 87 PIT Channel 3 |
|
|
|
pdb_isr, // 88 PDB Programmable Delay Block |
|
|
|
usb_isr, // 89 USB OTG |
|
|
|
usb_charge_isr, // 90 USB Charger Detect |
|
|
|
unused_isr, // 91 -- |
|
|
|
unused_isr, // 92 -- |
|
|
|
unused_isr, // 93 -- |
|
|
|
unused_isr, // 94 -- |
|
|
|
unused_isr, // 95 -- |
|
|
|
unused_isr, // 96 -- |
|
|
|
dac0_isr, // 97 DAC0 |
|
|
|
unused_isr, // 98 -- |
|
|
|
tsi0_isr, // 99 TSI0 |
|
|
|
mcg_isr, // 100 MCG |
|
|
|
lptmr_isr, // 101 Low Power Timer |
|
|
|
unused_isr, // 102 -- |
|
|
|
porta_isr, // 103 Pin detect (Port A) |
|
|
|
portb_isr, // 104 Pin detect (Port B) |
|
|
|
portc_isr, // 105 Pin detect (Port C) |
|
|
|
portd_isr, // 106 Pin detect (Port D) |
|
|
|
porte_isr, // 107 Pin detect (Port E) |
|
|
|
unused_isr, // 108 -- |
|
|
|
unused_isr, // 109 -- |
|
|
|
software_isr, // 110 Software interrupt |
|
|
|
dma_ch0_isr, // 16 DMA channel 0 transfer complete |
|
|
|
dma_ch1_isr, // 17 DMA channel 1 transfer complete |
|
|
|
dma_ch2_isr, // 18 DMA channel 2 transfer complete |
|
|
|
dma_ch3_isr, // 19 DMA channel 3 transfer complete |
|
|
|
dma_ch4_isr, // 20 DMA channel 4 transfer complete |
|
|
|
dma_ch5_isr, // 21 DMA channel 5 transfer complete |
|
|
|
dma_ch6_isr, // 22 DMA channel 6 transfer complete |
|
|
|
dma_ch7_isr, // 23 DMA channel 7 transfer complete |
|
|
|
dma_ch8_isr, // 24 DMA channel 8 transfer complete |
|
|
|
dma_ch9_isr, // 25 DMA channel 9 transfer complete |
|
|
|
dma_ch10_isr, // 26 DMA channel 10 transfer complete |
|
|
|
dma_ch11_isr, // 27 DMA channel 10 transfer complete |
|
|
|
dma_ch12_isr, // 28 DMA channel 10 transfer complete |
|
|
|
dma_ch13_isr, // 29 DMA channel 10 transfer complete |
|
|
|
dma_ch14_isr, // 30 DMA channel 10 transfer complete |
|
|
|
dma_ch15_isr, // 31 DMA channel 10 transfer complete |
|
|
|
dma_error_isr, // 32 DMA error interrupt channel |
|
|
|
unused_isr, // 33 -- |
|
|
|
flash_cmd_isr, // 34 Flash Memory Command complete |
|
|
|
flash_error_isr, // 35 Flash Read collision |
|
|
|
low_voltage_isr, // 36 Low-voltage detect/warning |
|
|
|
wakeup_isr, // 37 Low Leakage Wakeup |
|
|
|
watchdog_isr, // 38 Both EWM and WDOG interrupt |
|
|
|
unused_isr, // 39 -- |
|
|
|
i2c0_isr, // 40 I2C0 |
|
|
|
i2c1_isr, // 41 I2C1 |
|
|
|
spi0_isr, // 42 SPI0 |
|
|
|
spi1_isr, // 43 SPI1 |
|
|
|
unused_isr, // 44 -- |
|
|
|
can0_message_isr, // 45 CAN OR'ed Message buffer (0-15) |
|
|
|
can0_bus_off_isr, // 46 CAN Bus Off |
|
|
|
can0_error_isr, // 47 CAN Error |
|
|
|
can0_tx_warn_isr, // 48 CAN Transmit Warning |
|
|
|
can0_rx_warn_isr, // 49 CAN Receive Warning |
|
|
|
can0_wakeup_isr, // 50 CAN Wake Up |
|
|
|
i2s0_tx_isr, // 51 I2S0 Transmit |
|
|
|
i2s0_rx_isr, // 52 I2S0 Receive |
|
|
|
unused_isr, // 53 -- |
|
|
|
unused_isr, // 54 -- |
|
|
|
unused_isr, // 55 -- |
|
|
|
unused_isr, // 56 -- |
|
|
|
unused_isr, // 57 -- |
|
|
|
unused_isr, // 58 -- |
|
|
|
unused_isr, // 59 -- |
|
|
|
uart0_lon_isr, // 60 UART0 CEA709.1-B (LON) status |
|
|
|
uart0_status_isr, // 61 UART0 status |
|
|
|
uart0_error_isr, // 62 UART0 error |
|
|
|
uart1_status_isr, // 63 UART1 status |
|
|
|
uart1_error_isr, // 64 UART1 error |
|
|
|
uart2_status_isr, // 65 UART2 status |
|
|
|
uart2_error_isr, // 66 UART2 error |
|
|
|
unused_isr, // 67 -- |
|
|
|
unused_isr, // 68 -- |
|
|
|
unused_isr, // 69 -- |
|
|
|
unused_isr, // 70 -- |
|
|
|
unused_isr, // 71 -- |
|
|
|
unused_isr, // 72 -- |
|
|
|
adc0_isr, // 73 ADC0 |
|
|
|
adc1_isr, // 74 ADC1 |
|
|
|
cmp0_isr, // 75 CMP0 |
|
|
|
cmp1_isr, // 76 CMP1 |
|
|
|
cmp2_isr, // 77 CMP2 |
|
|
|
ftm0_isr, // 78 FTM0 |
|
|
|
ftm1_isr, // 79 FTM1 |
|
|
|
ftm2_isr, // 80 FTM2 |
|
|
|
cmt_isr, // 81 CMT |
|
|
|
rtc_alarm_isr, // 82 RTC Alarm interrupt |
|
|
|
rtc_seconds_isr, // 83 RTC Seconds interrupt |
|
|
|
pit0_isr, // 84 PIT Channel 0 |
|
|
|
pit1_isr, // 85 PIT Channel 1 |
|
|
|
pit2_isr, // 86 PIT Channel 2 |
|
|
|
pit3_isr, // 87 PIT Channel 3 |
|
|
|
pdb_isr, // 88 PDB Programmable Delay Block |
|
|
|
usb_isr, // 89 USB OTG |
|
|
|
usb_charge_isr, // 90 USB Charger Detect |
|
|
|
unused_isr, // 91 -- |
|
|
|
unused_isr, // 92 -- |
|
|
|
unused_isr, // 93 -- |
|
|
|
unused_isr, // 94 -- |
|
|
|
unused_isr, // 95 -- |
|
|
|
unused_isr, // 96 -- |
|
|
|
dac0_isr, // 97 DAC0 |
|
|
|
unused_isr, // 98 -- |
|
|
|
tsi0_isr, // 99 TSI0 |
|
|
|
mcg_isr, // 100 MCG |
|
|
|
lptmr_isr, // 101 Low Power Timer |
|
|
|
unused_isr, // 102 -- |
|
|
|
porta_isr, // 103 Pin detect (Port A) |
|
|
|
portb_isr, // 104 Pin detect (Port B) |
|
|
|
portc_isr, // 105 Pin detect (Port C) |
|
|
|
portd_isr, // 106 Pin detect (Port D) |
|
|
|
porte_isr, // 107 Pin detect (Port E) |
|
|
|
unused_isr, // 108 -- |
|
|
|
unused_isr, // 109 -- |
|
|
|
software_isr, // 110 Software interrupt |
|
|
|
#endif |
|
|
|
}; |
|
|
|
|
|
|
|
|
|
|
|
#if defined(_mk20dx128_) || defined(_mk20dx256_) |
|
|
|
// ----- Flash Configuration ----- |
|
|
|
|
|
|
|
// Only necessary for Teensy 3s, MCHCK uses the Bootloader to handle this |
|
|
|
#if defined(_mk20dx128_) || defined(_mk20dx256_) |
|
|
|
__attribute__ ((section(".flashconfig"), used)) |
|
|
|
const uint8_t flashconfigbytes[16] = { |
|
|
|
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, |
|
|
|
0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF |
|
|
|
}; |
|
|
|
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
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// Automatically initialize the RTC. When the build defines the compile |
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// time, and the user has added a crystal, the RTC will automatically |
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// begin at the time of the first upload. |
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#ifndef TIME_T |
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#define TIME_T 1349049600 // default 1 Oct 2012 (never used, Arduino sets this) |
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#endif |
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extern void rtc_set(unsigned long t); |
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// ----- Chip Entry Point ----- |
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__attribute__ ((section(".startup"))) |
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void ResetHandler(void) |
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void ResetHandler() |
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{ |
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uint32_t *src = &_etext; |
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uint32_t *dest = &_sdata; |
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unsigned int i; |
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/* Disable Watchdog */ |
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WDOG_UNLOCK = WDOG_UNLOCK_SEQ1; |
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@@ -370,141 +380,167 @@ void ResetHandler(void) |
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SIM_SCGC6 = SIM_SCGC6_RTC | SIM_SCGC6_FTM0 | SIM_SCGC6_FTM1 | SIM_SCGC6_ADC0 | SIM_SCGC6_FTFL; |
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#endif |
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#if defined(_mk20dx128_) || defined(_mk20dx256_) // Teensy 3s |
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// if the RTC oscillator isn't enabled, get it started early |
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if (!(RTC_CR & RTC_CR_OSCE)) { |
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if ( !(RTC_CR & RTC_CR_OSCE) ) |
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{ |
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RTC_SR = 0; |
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RTC_CR = RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE; |
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} |
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#endif |
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// release I/O pins hold, if we woke up from VLLS mode |
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if (PMC_REGSC & PMC_REGSC_ACKISO) PMC_REGSC |= PMC_REGSC_ACKISO; |
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// TODO: do this while the PLL is waiting to lock.... |
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while (dest < &_edata) *dest++ = *src++; |
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// Prepare RAM |
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while ( dest < &_edata ) *dest++ = *src++; |
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dest = &_sbss; |
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while (dest < &_ebss) *dest++ = 0; |
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SCB_VTOR = 0; // use vector table in flash |
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// default all interrupts to medium priority level |
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for (i=0; i < NVIC_NUM_INTERRUPTS; i++) NVIC_SET_PRIORITY(i, 128); |
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while ( dest < &_ebss ) *dest++ = 0; |
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// MCHCK |
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#if defined(_mk20dx128vlf5_) |
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/* FLL at 48MHz */ |
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MCG_C4 = MCG_C4_DMX32 | MCG_C4_DRST_DRS(1); |
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MCG_C4 = MCG_C4_DMX32 | MCG_C4_DRST_DRS( 1 ); |
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#if F_CPU == 96000000 |
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// config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3); |
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#elif F_CPU == 48000000 |
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// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3); |
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#elif F_CPU == 24000000 |
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// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(3); |
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#else |
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#error "Error, F_CPU must be 96000000, 48000000, or 24000000" |
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#endif |
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//SIM_SOPT2 = SIM_SOPT2_PLLFLLSEL; |
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SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL( 6 ); |
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// switch to PLL as clock source, FLL input = 16 MHz / 512 |
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MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4); |
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// Teensy 3.0 and 3.1 |
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#else |
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unsigned int i; |
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// configure USB for 48 MHz clock |
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SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2 |
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SCB_VTOR = 0; // use vector table in flash |
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SIM_SOPT2 = SIM_SOPT2_PLLFLLSEL; |
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// default all interrupts to medium priority level |
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for ( i = 0; i < NVIC_NUM_INTERRUPTS; i++ ) |
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{ |
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NVIC_SET_PRIORITY( i, 128 ); |
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} |
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// initialize the SysTick counter |
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SYST_RVR = (F_CPU / 1000) - 1; |
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SYST_CSR = SYST_CSR_CLKSOURCE | SYST_CSR_TICKINT | SYST_CSR_ENABLE; |
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#else |
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// start in FEI mode |
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// enable capacitors for crystal |
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OSC0_CR = OSC_SC8P | OSC_SC2P; |
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// enable osc, 8-32 MHz range, low power mode |
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MCG_C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS; |
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MCG_C2 = MCG_C2_RANGE0( 2 ) | MCG_C2_EREFS; |
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// switch to crystal as clock source, FLL input = 16 MHz / 512 |
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MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(4); |
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MCG_C1 = MCG_C1_CLKS( 2 ) | MCG_C1_FRDIV( 4 ); |
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// wait for crystal oscillator to begin |
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while ((MCG_S & MCG_S_OSCINIT0) == 0) ; |
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while ( (MCG_S & MCG_S_OSCINIT0) == 0 ); |
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// wait for FLL to use oscillator |
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while ((MCG_S & MCG_S_IREFST) != 0) ; |
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while ( (MCG_S & MCG_S_IREFST) != 0 ); |
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// wait for MCGOUT to use oscillator |
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while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2)) ; |
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while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 2 ) ); |
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// now we're in FBE mode |
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// config PLL input for 16 MHz Crystal / 4 = 4 MHz |
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MCG_C5 = MCG_C5_PRDIV0(3); |
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MCG_C5 = MCG_C5_PRDIV0( 3 ); |
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// config PLL for 96 MHz output |
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MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0); |
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MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0( 0 ); |
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// wait for PLL to start using xtal as its input |
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while (!(MCG_S & MCG_S_PLLST)) ; |
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while ( !(MCG_S & MCG_S_PLLST) ); |
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// wait for PLL to lock |
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while (!(MCG_S & MCG_S_LOCK0)) ; |
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while ( !(MCG_S & MCG_S_LOCK0) ); |
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// now we're in PBE mode |
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#if F_CPU == 96000000 |
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// config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3); |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 0 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 ); |
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#elif F_CPU == 48000000 |
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// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(1) | SIM_CLKDIV1_OUTDIV4(3); |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 1 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 ); |
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#elif F_CPU == 24000000 |
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// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(3) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV4(3); |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 3 ) | SIM_CLKDIV1_OUTDIV2( 3 ) | SIM_CLKDIV1_OUTDIV4( 3 ); |
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#else |
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#error "Error, F_CPU must be 96000000, 48000000, or 24000000" |
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#endif |
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// switch to PLL as clock source, FLL input = 16 MHz / 512 |
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MCG_C1 = MCG_C1_CLKS(0) | MCG_C1_FRDIV(4); |
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MCG_C1 = MCG_C1_CLKS( 0 ) | MCG_C1_FRDIV( 4 ); |
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// wait for PLL clock to be used |
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while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST(3)) ; |
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while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 3 ) ); |
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// now we're in PEE mode |
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// configure USB for 48 MHz clock |
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SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV(1); // USB = 96 MHz PLL / 2 |
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SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV( 1 ); // USB = 96 MHz PLL / 2 |
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// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0 |
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SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL(6); |
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SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL( 6 ); |
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// initialize the SysTick counter |
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#endif |
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// Initialize the SysTick counter |
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SYST_RVR = (F_CPU / 1000) - 1; |
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SYST_CSR = SYST_CSR_CLKSOURCE | SYST_CSR_TICKINT | SYST_CSR_ENABLE; |
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#endif |
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__enable_irq(); |
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__libc_init_array(); |
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main(); |
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while (1) ; |
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while ( 1 ); // Shouldn't get here... |
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} |
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// ----- RAM Setup ----- |
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char *__brkval = (char *)&_ebss; |
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void * _sbrk(int incr) |
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void * _sbrk( int incr ) |
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{ |
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//static char *heap_end = (char *)&_ebss; |
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//char *prev = heap_end; |
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//heap_end += incr; |
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char *prev = __brkval; |
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__brkval += incr; |
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return prev; |
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} |
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int nvic_execution_priority(void) |
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// ----- Interrupt Execution Priority ----- |
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int nvic_execution_priority() |
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{ |
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int priority=256; |
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int priority = 256; |
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uint32_t primask, faultmask, basepri, ipsr; |
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// full algorithm in ARM DDI0403D, page B1-639 |
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// this isn't quite complete, but hopefully good enough |
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asm volatile("mrs %0, faultmask\n" : "=r" (faultmask)::); |
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if (faultmask) return -1; |
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asm volatile("mrs %0, primask\n" : "=r" (primask)::); |
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if (primask) return 0; |
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asm volatile("mrs %0, ipsr\n" : "=r" (ipsr)::); |
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if (ipsr) { |
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if (ipsr < 16) priority = 0; // could be non-zero |
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else priority = NVIC_GET_PRIORITY(ipsr - 16); |
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asm volatile( "mrs %0, faultmask\n" : "=r" (faultmask):: ); |
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if ( faultmask ) |
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{ |
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return -1; |
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} |
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asm volatile( "mrs %0, primask\n" : "=r" (primask):: ); |
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if ( primask ) |
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{ |
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return 0; |
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} |
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asm volatile( "mrs %0, ipsr\n" : "=r" (ipsr):: ); |
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if ( ipsr ) |
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{ |
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if ( ipsr < 16) |
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{ |
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priority = 0; // could be non-zero |
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} |
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else |
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{ |
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priority = NVIC_GET_PRIORITY( ipsr - 16 ); |
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} |
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} |
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asm volatile( "mrs %0, basepri\n" : "=r" (basepri):: ); |
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if ( basepri > 0 && basepri < priority ) |
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{ |
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priority = basepri; |
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} |
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asm volatile("mrs %0, basepri\n" : "=r" (basepri)::); |
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if (basepri > 0 && basepri < priority) priority = basepri; |
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return priority; |
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} |
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