699 lines
31 KiB
C
699 lines
31 KiB
C
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/*******************************************************************************
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* DISCLAIMER
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* This software is supplied by Renesas Electronics Corporation and is only
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* intended for use with Renesas products. No other uses are authorized. This
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* software is owned by Renesas Electronics Corporation and is protected under
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* all applicable laws, including copyright laws.
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* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
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* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
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* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
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* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
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* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
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* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
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* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
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* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
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* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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* Renesas reserves the right, without notice, to make changes to this software
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* and to discontinue the availability of this software. By using this software,
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* you agree to the additional terms and conditions found by accessing the
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* following link:
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* http://www.renesas.com/disclaimer
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* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
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*******************************************************************************/
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/*******************************************************************************
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* File Name : usb1_function_dmacdrv.c
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* $Rev: 1116 $
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* $Date:: 2014-07-09 16:29:19 +0900#$
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* Device(s) : RZ/A1H
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* Tool-Chain :
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* OS : None
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* H/W Platform :
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* Description : RZ/A1H R7S72100 USB Sample Program
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* Operation :
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* Limitations :
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*******************************************************************************/
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/*******************************************************************************
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Includes <System Includes> , "Project Includes"
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*******************************************************************************/
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#include <stdio.h>
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#include "r_typedefs.h"
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#include "iodefine.h"
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#include "rza_io_regrw.h"
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#include "usb1_function_dmacdrv.h"
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/*******************************************************************************
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Typedef definitions
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*******************************************************************************/
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/*******************************************************************************
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Macro definitions
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*******************************************************************************/
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#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
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/* ==== Request setting information for on-chip peripheral module ==== */
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typedef enum dmac_peri_req_reg_type
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{
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DMAC_REQ_MID,
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DMAC_REQ_RID,
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DMAC_REQ_AM,
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DMAC_REQ_LVL,
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DMAC_REQ_REQD
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} dmac_peri_req_reg_type_t;
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/*******************************************************************************
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Imported global variables and functions (from other files)
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*******************************************************************************/
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/*******************************************************************************
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Exported global variables and functions (to be accessed by other files)
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*******************************************************************************/
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/*******************************************************************************
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Private global variables and functions
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*******************************************************************************/
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/* ==== Prototype declaration ==== */
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/* ==== Global variable ==== */
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/* On-chip peripheral module request setting table */
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static const uint8_t usb1_function_dmac_peri_req_init_table[8][5] =
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{
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/* MID,RID,AM,LVL,REQD */
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{32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
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{32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
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{33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
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{33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
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{34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
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{34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
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{35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
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{35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
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};
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/*******************************************************************************
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* Function Name: usb1_function_DMAC3_PeriReqInit
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* Description : Sets the register mode for DMA mode and the on-chip peripheral
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* : module request for transfer request for DMAC channel 1.
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* : Executes DMAC initial setting using the DMA information
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* : specified by the argument *trans_info and the enabled/disabled
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* : continuous transfer specified by the argument continuation.
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* : Registers DMAC channel 1 interrupt handler function and sets
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* : the interrupt priority level. Then enables transfer completion
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* : interrupt.
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* Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register
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* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
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* : uint32_t continuation : Set continuous transfer to be valid
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* : after DMA transfer has been completed
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* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
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* : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer
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* : uint32_t request_factor : Factor for on-chip peripheral module request
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* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
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* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
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* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
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* : :
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* : uint32_t req_direction: Setting value of CHCFG_n register REQD bit
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* Return Value : none
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*******************************************************************************/
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void usb1_function_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info,
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uint32_t dmamode, uint32_t continuation,
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uint32_t request_factor, uint32_t req_direction)
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{
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/* ==== Register mode ==== */
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if (DMAC_MODE_REGISTER == dmamode)
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{
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/* ==== Next0 register set ==== */
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DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
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DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
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DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */
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/* DAD : Transfer destination address counting direction */
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/* SAD : Transfer source address counting direction */
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/* DDS : Transfer destination transfer size */
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/* SDS : Transfer source transfer size */
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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trans_info->daddr_dir,
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DMAC3_CHCFG_n_DAD_SHIFT,
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DMAC3_CHCFG_n_DAD);
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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trans_info->saddr_dir,
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DMAC3_CHCFG_n_SAD_SHIFT,
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DMAC3_CHCFG_n_SAD);
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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trans_info->dst_size,
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DMAC3_CHCFG_n_DDS_SHIFT,
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DMAC3_CHCFG_n_DDS);
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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trans_info->src_size,
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DMAC3_CHCFG_n_SDS_SHIFT,
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DMAC3_CHCFG_n_SDS);
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/* DMS : Register mode */
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/* RSEL : Select Next0 register set */
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/* SBE : No discharge of buffer data when aborted */
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/* DEM : No DMA interrupt mask */
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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0,
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DMAC3_CHCFG_n_DMS_SHIFT,
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DMAC3_CHCFG_n_DMS);
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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0,
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DMAC3_CHCFG_n_RSEL_SHIFT,
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DMAC3_CHCFG_n_RSEL);
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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0,
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DMAC3_CHCFG_n_SBE_SHIFT,
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DMAC3_CHCFG_n_SBE);
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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0,
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DMAC3_CHCFG_n_DEM_SHIFT,
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DMAC3_CHCFG_n_DEM);
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/* ---- Continuous transfer ---- */
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if (DMAC_SAMPLE_CONTINUATION == continuation)
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{
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/* REN : Execute continuous transfer */
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/* RSW : Change register set when DMA transfer is completed. */
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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1,
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DMAC3_CHCFG_n_REN_SHIFT,
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DMAC3_CHCFG_n_REN);
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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1,
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DMAC3_CHCFG_n_RSW_SHIFT,
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DMAC3_CHCFG_n_RSW);
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}
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/* ---- Single transfer ---- */
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else
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{
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/* REN : Do not execute continuous transfer */
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/* RSW : Do not change register set when DMA transfer is completed. */
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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0,
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DMAC3_CHCFG_n_REN_SHIFT,
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DMAC3_CHCFG_n_REN);
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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0,
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DMAC3_CHCFG_n_RSW_SHIFT,
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DMAC3_CHCFG_n_RSW);
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}
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/* TM : Single transfer */
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/* SEL : Channel setting */
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/* HIEN, LOEN : On-chip peripheral module request */
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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0,
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DMAC3_CHCFG_n_TM_SHIFT,
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DMAC3_CHCFG_n_TM);
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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3,
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DMAC3_CHCFG_n_SEL_SHIFT,
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DMAC3_CHCFG_n_SEL);
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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1,
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DMAC3_CHCFG_n_HIEN_SHIFT,
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DMAC3_CHCFG_n_HIEN);
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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0,
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DMAC3_CHCFG_n_LOEN_SHIFT,
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DMAC3_CHCFG_n_LOEN);
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/* ---- Set factor by specified on-chip peripheral module request ---- */
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
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DMAC3_CHCFG_n_AM_SHIFT,
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DMAC3_CHCFG_n_AM);
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
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DMAC3_CHCFG_n_LVL_SHIFT,
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DMAC3_CHCFG_n_LVL);
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if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
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{
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
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DMAC3_CHCFG_n_REQD_SHIFT,
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DMAC3_CHCFG_n_REQD);
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}
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else
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{
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RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
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req_direction,
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DMAC3_CHCFG_n_REQD_SHIFT,
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DMAC3_CHCFG_n_REQD);
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}
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RZA_IO_RegWrite_32(&DMAC23.DMARS,
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usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
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DMAC23_DMARS_CH3_RID_SHIFT,
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DMAC23_DMARS_CH3_RID);
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RZA_IO_RegWrite_32(&DMAC23.DMARS,
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usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
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DMAC23_DMARS_CH3_MID_SHIFT,
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DMAC23_DMARS_CH3_MID);
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/* PR : Round robin mode */
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RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
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1,
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DMAC07_DCTRL_0_7_PR_SHIFT,
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DMAC07_DCTRL_0_7_PR);
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}
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}
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/*******************************************************************************
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* Function Name: usb1_function_DMAC3_Open
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* Description : Enables DMAC channel 3 transfer.
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* Arguments : uint32_t req : DMAC request mode
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* Return Value : 0 : Succeeded in enabling DMA transfer
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* : -1 : Failed to enable DMA transfer (due to DMA operation)
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*******************************************************************************/
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int32_t usb1_function_DMAC3_Open (uint32_t req)
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{
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int32_t ret;
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volatile uint8_t dummy;
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/* Transferable? */
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if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
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DMAC3_CHSTAT_n_EN_SHIFT,
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DMAC3_CHSTAT_n_EN)) &&
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(0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
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DMAC3_CHSTAT_n_TACT_SHIFT,
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DMAC3_CHSTAT_n_TACT)))
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{
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/* Clear Channel Status Register */
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RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
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1,
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DMAC3_CHCTRL_n_SWRST_SHIFT,
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DMAC3_CHCTRL_n_SWRST);
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dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n,
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DMAC3_CHCTRL_n_SWRST_SHIFT,
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DMAC3_CHCTRL_n_SWRST);
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/* Enable DMA transfer */
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RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
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1,
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DMAC3_CHCTRL_n_SETEN_SHIFT,
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DMAC3_CHCTRL_n_SETEN);
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/* ---- Request by software ---- */
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if (DMAC_REQ_MODE_SOFT == req)
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{
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/* DMA transfer Request by software */
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RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
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1,
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DMAC3_CHCTRL_n_STG_SHIFT,
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DMAC3_CHCTRL_n_STG);
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}
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ret = 0;
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}
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else
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{
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ret = -1;
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}
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return ret;
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}
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/*******************************************************************************
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|
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* Function Name: usb1_function_DMAC3_Close
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* Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer
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* : byte count at the time of DMA transfer abort to the argument
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* : *remain.
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* Arguments : uint32_t * remain : Remaining transfer byte count when
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* : : DMA transfer is aborted
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* Return Value : none
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*******************************************************************************/
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void usb1_function_DMAC3_Close (uint32_t * remain)
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{
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/* ==== Abort transfer ==== */
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||
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RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
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1,
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DMAC3_CHCTRL_n_CLREN_SHIFT,
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|
|
DMAC3_CHCTRL_n_CLREN);
|
||
|
|
|
||
|
|
while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||
|
|
DMAC3_CHSTAT_n_TACT_SHIFT,
|
||
|
|
DMAC3_CHSTAT_n_TACT))
|
||
|
|
{
|
||
|
|
/* Loop until transfer is aborted */
|
||
|
|
}
|
||
|
|
|
||
|
|
while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||
|
|
DMAC3_CHSTAT_n_EN_SHIFT,
|
||
|
|
DMAC3_CHSTAT_n_EN))
|
||
|
|
{
|
||
|
|
/* Loop until 0 is set in EN before checking the remaining transfer byte count */
|
||
|
|
}
|
||
|
|
/* ==== Obtain remaining transfer byte count ==== */
|
||
|
|
*remain = DMAC3.CRTB_n;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Function Name: usb1_function_DMAC3_Load_Set
|
||
|
|
* Description : Sets the transfer source address, transfer destination
|
||
|
|
* : address, and total transfer byte count respectively
|
||
|
|
* : specified by the argument src_addr, dst_addr, and count to
|
||
|
|
* : DMAC channel 3 as DMA transfer information.
|
||
|
|
* : Sets the register set selected by the CHCFG_n register
|
||
|
|
* : RSEL bit from the Next0 or Next1 register set.
|
||
|
|
* : This function should be called when DMA transfer of DMAC
|
||
|
|
* : channel 3 is aboted.
|
||
|
|
* Arguments : uint32_t src_addr : Transfer source address
|
||
|
|
* : uint32_t dst_addr : Transfer destination address
|
||
|
|
* : uint32_t count : Total transfer byte count
|
||
|
|
* Return Value : none
|
||
|
|
*******************************************************************************/
|
||
|
|
void usb1_function_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
|
||
|
|
{
|
||
|
|
uint8_t reg_set;
|
||
|
|
|
||
|
|
/* Obtain register set in use */
|
||
|
|
reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
|
||
|
|
DMAC3_CHSTAT_n_SR_SHIFT,
|
||
|
|
DMAC3_CHSTAT_n_SR);
|
||
|
|
|
||
|
|
/* ==== Load ==== */
|
||
|
|
if (0 == reg_set)
|
||
|
|
{
|
||
|
|
/* ---- Next0 Register Set ---- */
|
||
|
|
DMAC3.N0SA_n = src_addr; /* Start address of transfer source */
|
||
|
|
DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */
|
||
|
|
DMAC3.N0TB_n = count; /* Total transfer byte count */
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* ---- Next1 Register Set ---- */
|
||
|
|
DMAC3.N1SA_n = src_addr; /* Start address of transfer source */
|
||
|
|
DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */
|
||
|
|
DMAC3.N1TB_n = count; /* Total transfer byte count */
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Function Name: usb1_function_DMAC4_PeriReqInit
|
||
|
|
* Description : Sets the register mode for DMA mode and the on-chip peripheral
|
||
|
|
* : module request for transfer request for DMAC channel 2.
|
||
|
|
* : Executes DMAC initial setting using the DMA information
|
||
|
|
* : specified by the argument *trans_info and the enabled/disabled
|
||
|
|
* : continuous transfer specified by the argument continuation.
|
||
|
|
* : Registers DMAC channel 2 interrupt handler function and sets
|
||
|
|
* : the interrupt priority level. Then enables transfer completion
|
||
|
|
* : interrupt.
|
||
|
|
* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
|
||
|
|
* : : register
|
||
|
|
* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
|
||
|
|
* : uint32_t continuation : Set continuous transfer to be valid
|
||
|
|
* : : after DMA transfer has been completed
|
||
|
|
* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
|
||
|
|
* : DMAC_SAMPLE_SINGLE : Do not execute continuous
|
||
|
|
* : : transfer
|
||
|
|
* : uint32_t request_factor : Factor for on-chip peripheral module
|
||
|
|
* : : request
|
||
|
|
* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
|
||
|
|
* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
|
||
|
|
* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
|
||
|
|
* : :
|
||
|
|
* : uint32_t req_direction : Setting value of CHCFG_n register
|
||
|
|
* : : REQD bit
|
||
|
|
*******************************************************************************/
|
||
|
|
void usb1_function_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info,
|
||
|
|
uint32_t dmamode, uint32_t continuation,
|
||
|
|
uint32_t request_factor, uint32_t req_direction)
|
||
|
|
{
|
||
|
|
/* ==== Register mode ==== */
|
||
|
|
if (DMAC_MODE_REGISTER == dmamode)
|
||
|
|
{
|
||
|
|
/* ==== Next0 register set ==== */
|
||
|
|
DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
|
||
|
|
DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
|
||
|
|
DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */
|
||
|
|
|
||
|
|
/* DAD : Transfer destination address counting direction */
|
||
|
|
/* SAD : Transfer source address counting direction */
|
||
|
|
/* DDS : Transfer destination transfer size */
|
||
|
|
/* SDS : Transfer source transfer size */
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
trans_info->daddr_dir,
|
||
|
|
DMAC4_CHCFG_n_DAD_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_DAD);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
trans_info->saddr_dir,
|
||
|
|
DMAC4_CHCFG_n_SAD_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_SAD);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
trans_info->dst_size,
|
||
|
|
DMAC4_CHCFG_n_DDS_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_DDS);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
trans_info->src_size,
|
||
|
|
DMAC4_CHCFG_n_SDS_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_SDS);
|
||
|
|
|
||
|
|
/* DMS : Register mode */
|
||
|
|
/* RSEL : Select Next0 register set */
|
||
|
|
/* SBE : No discharge of buffer data when aborted */
|
||
|
|
/* DEM : No DMA interrupt mask */
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
0,
|
||
|
|
DMAC4_CHCFG_n_DMS_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_DMS);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
0,
|
||
|
|
DMAC4_CHCFG_n_RSEL_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_RSEL);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
0,
|
||
|
|
DMAC4_CHCFG_n_SBE_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_SBE);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
0,
|
||
|
|
DMAC4_CHCFG_n_DEM_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_DEM);
|
||
|
|
|
||
|
|
/* ---- Continuous transfer ---- */
|
||
|
|
if (DMAC_SAMPLE_CONTINUATION == continuation)
|
||
|
|
{
|
||
|
|
/* REN : Execute continuous transfer */
|
||
|
|
/* RSW : Change register set when DMA transfer is completed. */
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
1,
|
||
|
|
DMAC4_CHCFG_n_REN_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_REN);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
1,
|
||
|
|
DMAC4_CHCFG_n_RSW_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_RSW);
|
||
|
|
}
|
||
|
|
/* ---- Single transfer ---- */
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* REN : Do not execute continuous transfer */
|
||
|
|
/* RSW : Do not change register set when DMA transfer is completed. */
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
0,
|
||
|
|
DMAC4_CHCFG_n_REN_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_REN);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
0,
|
||
|
|
DMAC4_CHCFG_n_RSW_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_RSW);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* TM : Single transfer */
|
||
|
|
/* SEL : Channel setting */
|
||
|
|
/* HIEN, LOEN : On-chip peripheral module request */
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
0,
|
||
|
|
DMAC4_CHCFG_n_TM_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_TM);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
4,
|
||
|
|
DMAC4_CHCFG_n_SEL_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_SEL);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
1,
|
||
|
|
DMAC4_CHCFG_n_HIEN_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_HIEN);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
0,
|
||
|
|
DMAC4_CHCFG_n_LOEN_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_LOEN);
|
||
|
|
|
||
|
|
/* ---- Set factor by specified on-chip peripheral module request ---- */
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
|
||
|
|
DMAC4_CHCFG_n_AM_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_AM);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
|
||
|
|
DMAC4_CHCFG_n_LVL_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_LVL);
|
||
|
|
if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
|
||
|
|
{
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
|
||
|
|
DMAC4_CHCFG_n_REQD_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_REQD);
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
|
||
|
|
req_direction,
|
||
|
|
DMAC4_CHCFG_n_REQD_SHIFT,
|
||
|
|
DMAC4_CHCFG_n_REQD);
|
||
|
|
}
|
||
|
|
RZA_IO_RegWrite_32(&DMAC45.DMARS,
|
||
|
|
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
|
||
|
|
DMAC45_DMARS_CH4_RID_SHIFT,
|
||
|
|
DMAC45_DMARS_CH4_RID);
|
||
|
|
RZA_IO_RegWrite_32(&DMAC45.DMARS,
|
||
|
|
usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
|
||
|
|
DMAC45_DMARS_CH4_MID_SHIFT,
|
||
|
|
DMAC45_DMARS_CH4_MID);
|
||
|
|
|
||
|
|
/* PR : Round robin mode */
|
||
|
|
RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
|
||
|
|
1,
|
||
|
|
DMAC07_DCTRL_0_7_PR_SHIFT,
|
||
|
|
DMAC07_DCTRL_0_7_PR);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Function Name: usb1_function_DMAC4_Open
|
||
|
|
* Description : Enables DMAC channel 4 transfer.
|
||
|
|
* Arguments : uint32_t req : DMAC request mode
|
||
|
|
* Return Value : 0 : Succeeded in enabling DMA transfer
|
||
|
|
* : -1 : Failed to enable DMA transfer (due to DMA operation)
|
||
|
|
*******************************************************************************/
|
||
|
|
int32_t usb1_function_DMAC4_Open (uint32_t req)
|
||
|
|
{
|
||
|
|
int32_t ret;
|
||
|
|
volatile uint8_t dummy;
|
||
|
|
|
||
|
|
/* Transferable? */
|
||
|
|
if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||
|
|
DMAC4_CHSTAT_n_EN_SHIFT,
|
||
|
|
DMAC4_CHSTAT_n_EN)) &&
|
||
|
|
(0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||
|
|
DMAC4_CHSTAT_n_TACT_SHIFT,
|
||
|
|
DMAC4_CHSTAT_n_TACT)))
|
||
|
|
{
|
||
|
|
/* Clear Channel Status Register */
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
|
||
|
|
1,
|
||
|
|
DMAC4_CHCTRL_n_SWRST_SHIFT,
|
||
|
|
DMAC4_CHCTRL_n_SWRST);
|
||
|
|
dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n,
|
||
|
|
DMAC4_CHCTRL_n_SWRST_SHIFT,
|
||
|
|
DMAC4_CHCTRL_n_SWRST);
|
||
|
|
/* Enable DMA transfer */
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
|
||
|
|
1,
|
||
|
|
DMAC4_CHCTRL_n_SETEN_SHIFT,
|
||
|
|
DMAC4_CHCTRL_n_SETEN);
|
||
|
|
|
||
|
|
/* ---- Request by software ---- */
|
||
|
|
if (DMAC_REQ_MODE_SOFT == req)
|
||
|
|
{
|
||
|
|
/* DMA transfer Request by software */
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
|
||
|
|
1,
|
||
|
|
DMAC4_CHCTRL_n_STG_SHIFT,
|
||
|
|
DMAC4_CHCTRL_n_STG);
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = 0;
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
ret = -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Function Name: usb1_function_DMAC4_Close
|
||
|
|
* Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer
|
||
|
|
* : byte count at the time of DMA transfer abort to the argument
|
||
|
|
* : *remain.
|
||
|
|
* Arguments : uint32_t * remain : Remaining transfer byte count when
|
||
|
|
* : : DMA transfer is aborted
|
||
|
|
* Return Value : none
|
||
|
|
*******************************************************************************/
|
||
|
|
void usb1_function_DMAC4_Close (uint32_t * remain)
|
||
|
|
{
|
||
|
|
|
||
|
|
/* ==== Abort transfer ==== */
|
||
|
|
RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
|
||
|
|
1,
|
||
|
|
DMAC4_CHCTRL_n_CLREN_SHIFT,
|
||
|
|
DMAC4_CHCTRL_n_CLREN);
|
||
|
|
|
||
|
|
while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||
|
|
DMAC4_CHSTAT_n_TACT_SHIFT,
|
||
|
|
DMAC4_CHSTAT_n_TACT))
|
||
|
|
{
|
||
|
|
/* Loop until transfer is aborted */
|
||
|
|
}
|
||
|
|
|
||
|
|
while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
|
||
|
|
DMAC4_CHSTAT_n_EN_SHIFT,
|
||
|
|
DMAC4_CHSTAT_n_EN))
|
||
|
|
{
|
||
|
|
/* Loop until 0 is set in EN before checking the remaining transfer byte count */
|
||
|
|
}
|
||
|
|
/* ==== Obtain remaining transfer byte count ==== */
|
||
|
|
*remain = DMAC4.CRTB_n;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*******************************************************************************
|
||
|
|
* Function Name: usb1_function_DMAC4_Load_Set
|
||
|
|
* Description : Sets the transfer source address, transfer destination
|
||
|
|
* : address, and total transfer byte count respectively
|
||
|
|
* : specified by the argument src_addr, dst_addr, and count to
|
||
|
|
* : DMAC channel 4 as DMA transfer information.
|
||
|
|
* : Sets the register set selected by the CHCFG_n register
|
||
|
|
* : RSEL bit from the Next0 or Next1 register set.
|
||
|
|
* : This function should be called when DMA transfer of DMAC
|
||
|
|
* : channel 4 is aboted.
|
||
|
|
* Arguments : uint32_t src_addr : Transfer source address
|
||
|
|
* : uint32_t dst_addr : Transfer destination address
|
||
|
|
* : uint32_t count : Total transfer byte count
|
||
|
|
* Return Value : none
|
||
|
|
*******************************************************************************/
|
||
|
|
void usb1_function_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
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{
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uint8_t reg_set;
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/* Obtain register set in use */
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reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
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DMAC4_CHSTAT_n_SR_SHIFT,
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DMAC4_CHSTAT_n_SR);
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/* ==== Load ==== */
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if (0 == reg_set)
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{
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/* ---- Next0 Register Set ---- */
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DMAC4.N0SA_n = src_addr; /* Start address of transfer source */
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DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */
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DMAC4.N0TB_n = count; /* Total transfer byte count */
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}
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else
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{
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/* ---- Next1 Register Set ---- */
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DMAC4.N1SA_n = src_addr; /* Start address of transfer source */
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DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */
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DMAC4.N1TB_n = count; /* Total transfer byte count */
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}
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}
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/* End of File */
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