411 line
12 KiB
C++
411 line
12 KiB
C++
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/* Copyright (c) 2010-2011 mbed.org, MIT License
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
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* and associated documentation files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all copies or
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* substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#if defined(TARGET_STM32F4)
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#include "USBHAL.h"
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#include "USBRegs_STM32.h"
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#include "pinmap.h"
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USBHAL * USBHAL::instance;
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static volatile int epComplete = 0;
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static uint32_t bufferEnd = 0;
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static const uint32_t rxFifoSize = 512;
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static uint32_t rxFifoCount = 0;
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static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
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uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
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return 0;
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}
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USBHAL::USBHAL(void) {
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NVIC_DisableIRQ(OTG_FS_IRQn);
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epCallback[0] = &USBHAL::EP1_OUT_callback;
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epCallback[1] = &USBHAL::EP1_IN_callback;
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epCallback[2] = &USBHAL::EP2_OUT_callback;
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epCallback[3] = &USBHAL::EP2_IN_callback;
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epCallback[4] = &USBHAL::EP3_OUT_callback;
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epCallback[5] = &USBHAL::EP3_IN_callback;
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// Enable power and clocking
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RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
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#if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE)
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pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
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pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS));
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pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS));
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pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
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pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
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#else
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pin_function(PA_8, STM_PIN_DATA(2, 10));
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pin_function(PA_9, STM_PIN_DATA(0, 0));
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pin_function(PA_10, STM_PIN_DATA(2, 10));
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pin_function(PA_11, STM_PIN_DATA(2, 10));
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pin_function(PA_12, STM_PIN_DATA(2, 10));
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// Set ID pin to open drain with pull-up resistor
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pin_mode(PA_10, OpenDrain);
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GPIOA->PUPDR &= ~(0x3 << 20);
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GPIOA->PUPDR |= 1 << 20;
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// Set VBUS pin to open drain
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pin_mode(PA_9, OpenDrain);
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#endif
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RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
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// Enable interrupts
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OTG_FS->GREGS.GAHBCFG |= (1 << 0);
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// Turnaround time to maximum value - too small causes packet loss
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OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
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// Unmask global interrupts
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OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
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(1 << 4) | // RX FIFO not empty
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(1 << 12); // USB reset
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OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
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(1 << 2); // Non-zero-length status OUT handshake
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OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
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(1 << 16); // Power Up
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instance = this;
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NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
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NVIC_SetPriority(OTG_FS_IRQn, 1);
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}
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USBHAL::~USBHAL(void) {
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}
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void USBHAL::connect(void) {
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NVIC_EnableIRQ(OTG_FS_IRQn);
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}
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void USBHAL::disconnect(void) {
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NVIC_DisableIRQ(OTG_FS_IRQn);
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}
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void USBHAL::configureDevice(void) {
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// Not needed
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}
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void USBHAL::unconfigureDevice(void) {
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// Not needed
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}
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void USBHAL::setAddress(uint8_t address) {
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OTG_FS->DREGS.DCFG |= (address << 4);
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EP0write(0, 0);
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}
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bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
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uint32_t flags) {
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uint32_t epIndex = endpoint >> 1;
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uint32_t type;
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switch (endpoint) {
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case EP0IN:
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case EP0OUT:
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type = 0;
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break;
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case EPISO_IN:
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case EPISO_OUT:
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type = 1;
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case EPBULK_IN:
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case EPBULK_OUT:
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type = 2;
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break;
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case EPINT_IN:
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case EPINT_OUT:
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type = 3;
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break;
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}
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// Generic in or out EP controls
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uint32_t control = (maxPacket << 0) | // Packet size
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(1 << 15) | // Active endpoint
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(type << 18); // Endpoint type
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if (endpoint & 0x1) { // In Endpoint
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// Set up the Tx FIFO
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if (endpoint == EP0IN) {
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OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
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(bufferEnd << 0);
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}
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else {
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OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
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(bufferEnd << 0);
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}
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bufferEnd += maxPacket >> 2;
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// Set the In EP specific control settings
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if (endpoint != EP0IN) {
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control |= (1 << 28); // SD0PID
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}
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control |= (epIndex << 22) | // TxFIFO index
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(1 << 27); // SNAK
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OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
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// Unmask the interrupt
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OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
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}
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else { // Out endpoint
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// Set the out EP specific control settings
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control |= (1 << 26); // CNAK
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OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
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// Unmask the interrupt
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OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
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}
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return true;
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}
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// read setup packet
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void USBHAL::EP0setup(uint8_t *buffer) {
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memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
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}
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void USBHAL::EP0readStage(void) {
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}
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void USBHAL::EP0read(void) {
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}
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uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
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uint32_t* buffer32 = (uint32_t *) buffer;
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uint32_t length = rxFifoCount;
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for (uint32_t i = 0; i < length; i += 4) {
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buffer32[i >> 2] = OTG_FS->FIFO[0][0];
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}
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rxFifoCount = 0;
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return length;
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}
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void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
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endpointWrite(0, buffer, size);
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}
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void USBHAL::EP0getWriteResult(void) {
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}
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void USBHAL::EP0stall(void) {
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// If we stall the out endpoint here then we have problems transferring
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// and setup requests after the (stalled) get device qualifier requests.
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// TODO: Find out if this is correct behavior, or whether we are doing
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// something else wrong
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stallEndpoint(EP0IN);
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// stallEndpoint(EP0OUT);
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}
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EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
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uint32_t epIndex = endpoint >> 1;
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uint32_t size = (1 << 19) | // 1 packet
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(maximumSize << 0); // Packet size
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// if (endpoint == EP0OUT) {
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size |= (1 << 29); // 1 setup packet
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// }
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OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
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OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
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(1 << 26); // Clear NAK
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epComplete &= ~(1 << endpoint);
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return EP_PENDING;
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}
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EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
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if (!(epComplete & (1 << endpoint))) {
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return EP_PENDING;
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}
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uint32_t* buffer32 = (uint32_t *) buffer;
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uint32_t length = rxFifoCount;
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for (uint32_t i = 0; i < length; i += 4) {
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buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
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}
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rxFifoCount = 0;
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*bytesRead = length;
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return EP_COMPLETED;
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}
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EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
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uint32_t epIndex = endpoint >> 1;
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OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
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(size << 0); // Size of packet
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OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
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(1 << 26); // CNAK
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OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
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while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
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for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
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OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
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}
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epComplete &= ~(1 << endpoint);
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return EP_PENDING;
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}
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EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
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if (epComplete & (1 << endpoint)) {
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epComplete &= ~(1 << endpoint);
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return EP_COMPLETED;
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}
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return EP_PENDING;
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}
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void USBHAL::stallEndpoint(uint8_t endpoint) {
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if (endpoint & 0x1) { // In EP
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OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
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(1 << 21); // Stall
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}
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else { // Out EP
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OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
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OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
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(1 << 21); // Stall
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}
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}
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void USBHAL::unstallEndpoint(uint8_t endpoint) {
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}
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bool USBHAL::getEndpointStallState(uint8_t endpoint) {
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return false;
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}
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void USBHAL::remoteWakeup(void) {
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}
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void USBHAL::_usbisr(void) {
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instance->usbisr();
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}
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void USBHAL::usbisr(void) {
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if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
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// Set SNAK bits
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OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
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OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
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OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
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OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
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OTG_FS->DREGS.DIEPMSK = (1 << 0);
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bufferEnd = 0;
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// Set the receive FIFO size
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OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
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bufferEnd += rxFifoSize >> 2;
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// Create the endpoints, and wait for setup packets on out EP0
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realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
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realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
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endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
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OTG_FS->GREGS.GINTSTS = (1 << 12);
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}
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if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
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uint32_t status = OTG_FS->GREGS.GRXSTSP;
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uint32_t endpoint = (status & 0xF) << 1;
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uint32_t length = (status >> 4) & 0x7FF;
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uint32_t type = (status >> 17) & 0xF;
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rxFifoCount = length;
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if (type == 0x6) {
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// Setup packet
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for (uint32_t i=0; i<length; i+=4) {
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setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
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}
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rxFifoCount = 0;
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}
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if (type == 0x4) {
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// Setup complete
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EP0setupCallback();
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endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
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}
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if (type == 0x2) {
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// Out packet
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if (endpoint == EP0OUT) {
|
||
|
|
EP0out();
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
epComplete |= (1 << endpoint);
|
||
|
|
if ((instance->*(epCallback[endpoint - 2]))()) {
|
||
|
|
epComplete &= (1 << endpoint);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
for (uint32_t i=0; i<rxFifoCount; i+=4) {
|
||
|
|
(void) OTG_FS->FIFO[0][0];
|
||
|
|
}
|
||
|
|
OTG_FS->GREGS.GINTSTS = (1 << 4);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
|
||
|
|
// Loop through the in endpoints
|
||
|
|
for (uint32_t i=0; i<4; i++) {
|
||
|
|
if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
|
||
|
|
|
||
|
|
if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
|
||
|
|
// If the Tx FIFO is empty on EP0 we need to send a further
|
||
|
|
// packet, so call EP0in()
|
||
|
|
if (i == 0) {
|
||
|
|
EP0in();
|
||
|
|
}
|
||
|
|
// Clear the interrupt
|
||
|
|
OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
|
||
|
|
// Stop firing Tx empty interrupts
|
||
|
|
// Will get turned on again if another write is called
|
||
|
|
OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
|
||
|
|
}
|
||
|
|
|
||
|
|
// If the transfer is complete
|
||
|
|
if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
|
||
|
|
epComplete |= (1 << (1 + (i << 1)));
|
||
|
|
OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
OTG_FS->GREGS.GINTSTS = (1 << 18);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
|
||
|
|
SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
|
||
|
|
OTG_FS->GREGS.GINTSTS = (1 << 3);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
#endif
|