Add eeprom support for chibios/kinetis.
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flabbergast
parent
cb663eeca6
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551
tmk_core/common/chibios/eeconfig.c
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551
tmk_core/common/chibios/eeconfig.c
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@ -0,0 +1,551 @@
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#include "ch.h"
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#include "hal.h"
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#include "eeconfig.h"
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/*************************************/
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/* Hardware backend */
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/* */
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/* Code from PJRC/Teensyduino */
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/*************************************/
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/* Teensyduino Core Library
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* http://www.pjrc.com/teensy/
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* Copyright (c) 2013 PJRC.COM, LLC.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* 1. The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* 2. If the Software is incorporated into a build system that allows
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* selection among a list of target devices, then similar target
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* devices manufactured by PJRC.COM must be included in the list of
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* target devices and selectable in the same manner.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#if defined(K20x) /* chip selection */
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/* Teensy 3.0, 3.1, 3.2; mchck; infinity keyboard */
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// The EEPROM is really RAM with a hardware-based backup system to
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// flash memory. Selecting a smaller size EEPROM allows more wear
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// leveling, for higher write endurance. If you edit this file,
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// set this to the smallest size your application can use. Also,
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// due to Freescale's implementation, writing 16 or 32 bit words
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// (aligned to 2 or 4 byte boundaries) has twice the endurance
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// compared to writing 8 bit bytes.
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//
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#define EEPROM_SIZE 32
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// Writing unaligned 16 or 32 bit data is handled automatically when
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// this is defined, but at a cost of extra code size. Without this,
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// any unaligned write will cause a hard fault exception! If you're
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// absolutely sure all 16 and 32 bit writes will be aligned, you can
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// remove the extra unnecessary code.
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//
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#define HANDLE_UNALIGNED_WRITES
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// Minimum EEPROM Endurance
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// ------------------------
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#if (EEPROM_SIZE == 2048) // 35000 writes/byte or 70000 writes/word
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#define EEESIZE 0x33
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#elif (EEPROM_SIZE == 1024) // 75000 writes/byte or 150000 writes/word
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#define EEESIZE 0x34
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#elif (EEPROM_SIZE == 512) // 155000 writes/byte or 310000 writes/word
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#define EEESIZE 0x35
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#elif (EEPROM_SIZE == 256) // 315000 writes/byte or 630000 writes/word
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#define EEESIZE 0x36
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#elif (EEPROM_SIZE == 128) // 635000 writes/byte or 1270000 writes/word
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#define EEESIZE 0x37
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#elif (EEPROM_SIZE == 64) // 1275000 writes/byte or 2550000 writes/word
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#define EEESIZE 0x38
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#elif (EEPROM_SIZE == 32) // 2555000 writes/byte or 5110000 writes/word
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#define EEESIZE 0x39
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#endif
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void eeprom_initialize(void)
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{
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uint32_t count=0;
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uint16_t do_flash_cmd[] = {
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0xf06f, 0x037f, 0x7003, 0x7803,
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0xf013, 0x0f80, 0xd0fb, 0x4770};
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uint8_t status;
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if (FTFL->FCNFG & FTFL_FCNFG_RAMRDY) {
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// FlexRAM is configured as traditional RAM
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// We need to reconfigure for EEPROM usage
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FTFL->FCCOB0 = 0x80; // PGMPART = Program Partition Command
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FTFL->FCCOB4 = EEESIZE; // EEPROM Size
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FTFL->FCCOB5 = 0x03; // 0K for Dataflash, 32K for EEPROM backup
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__disable_irq();
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// do_flash_cmd() must execute from RAM. Luckily the C syntax is simple...
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(*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&(FTFL->FSTAT));
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__enable_irq();
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status = FTFL->FSTAT;
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if (status & (FTFL_FSTAT_RDCOLERR|FTFL_FSTAT_ACCERR|FTFL_FSTAT_FPVIOL)) {
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FTFL->FSTAT = (status & (FTFL_FSTAT_RDCOLERR|FTFL_FSTAT_ACCERR|FTFL_FSTAT_FPVIOL));
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return; // error
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}
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}
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// wait for eeprom to become ready (is this really necessary?)
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while (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) {
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if (++count > 20000) break;
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}
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}
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#define FlexRAM ((uint8_t *)0x14000000)
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uint8_t eeprom_read_byte(const uint8_t *addr)
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{
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE) return 0;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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return FlexRAM[offset];
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}
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uint16_t eeprom_read_word(const uint16_t *addr)
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{
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE-1) return 0;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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return *(uint16_t *)(&FlexRAM[offset]);
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}
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uint32_t eeprom_read_dword(const uint32_t *addr)
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{
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE-3) return 0;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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return *(uint32_t *)(&FlexRAM[offset]);
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}
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void eeprom_read_block(void *buf, const void *addr, uint32_t len)
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{
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uint32_t offset = (uint32_t)addr;
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uint8_t *dest = (uint8_t *)buf;
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uint32_t end = offset + len;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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if (end > EEPROM_SIZE) end = EEPROM_SIZE;
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while (offset < end) {
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*dest++ = FlexRAM[offset++];
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}
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}
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int eeprom_is_ready(void)
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{
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return (FTFL->FCNFG & FTFL_FCNFG_EEERDY) ? 1 : 0;
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}
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static void flexram_wait(void)
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{
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while (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) {
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// TODO: timeout
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}
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}
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void eeprom_write_byte(uint8_t *addr, uint8_t value)
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{
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE) return;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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if (FlexRAM[offset] != value) {
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FlexRAM[offset] = value;
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flexram_wait();
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}
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}
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void eeprom_write_word(uint16_t *addr, uint16_t value)
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{
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE-1) return;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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#ifdef HANDLE_UNALIGNED_WRITES
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if ((offset & 1) == 0) {
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#endif
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if (*(uint16_t *)(&FlexRAM[offset]) != value) {
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*(uint16_t *)(&FlexRAM[offset]) = value;
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flexram_wait();
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}
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#ifdef HANDLE_UNALIGNED_WRITES
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} else {
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if (FlexRAM[offset] != value) {
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FlexRAM[offset] = value;
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flexram_wait();
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}
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if (FlexRAM[offset + 1] != (value >> 8)) {
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FlexRAM[offset + 1] = value >> 8;
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flexram_wait();
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}
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}
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#endif
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}
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void eeprom_write_dword(uint32_t *addr, uint32_t value)
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{
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uint32_t offset = (uint32_t)addr;
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if (offset >= EEPROM_SIZE-3) return;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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#ifdef HANDLE_UNALIGNED_WRITES
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switch (offset & 3) {
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case 0:
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#endif
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if (*(uint32_t *)(&FlexRAM[offset]) != value) {
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*(uint32_t *)(&FlexRAM[offset]) = value;
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flexram_wait();
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}
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return;
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#ifdef HANDLE_UNALIGNED_WRITES
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case 2:
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if (*(uint16_t *)(&FlexRAM[offset]) != value) {
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*(uint16_t *)(&FlexRAM[offset]) = value;
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flexram_wait();
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}
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if (*(uint16_t *)(&FlexRAM[offset + 2]) != (value >> 16)) {
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*(uint16_t *)(&FlexRAM[offset + 2]) = value >> 16;
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flexram_wait();
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}
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return;
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default:
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if (FlexRAM[offset] != value) {
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FlexRAM[offset] = value;
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flexram_wait();
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}
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if (*(uint16_t *)(&FlexRAM[offset + 1]) != (value >> 8)) {
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*(uint16_t *)(&FlexRAM[offset + 1]) = value >> 8;
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flexram_wait();
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}
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if (FlexRAM[offset + 3] != (value >> 24)) {
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FlexRAM[offset + 3] = value >> 24;
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flexram_wait();
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}
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}
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#endif
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}
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void eeprom_write_block(const void *buf, void *addr, uint32_t len)
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{
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uint32_t offset = (uint32_t)addr;
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const uint8_t *src = (const uint8_t *)buf;
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if (offset >= EEPROM_SIZE) return;
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if (!(FTFL->FCNFG & FTFL_FCNFG_EEERDY)) eeprom_initialize();
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if (len >= EEPROM_SIZE) len = EEPROM_SIZE;
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if (offset + len >= EEPROM_SIZE) len = EEPROM_SIZE - offset;
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while (len > 0) {
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uint32_t lsb = offset & 3;
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if (lsb == 0 && len >= 4) {
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// write aligned 32 bits
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uint32_t val32;
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val32 = *src++;
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val32 |= (*src++ << 8);
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val32 |= (*src++ << 16);
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val32 |= (*src++ << 24);
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if (*(uint32_t *)(&FlexRAM[offset]) != val32) {
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*(uint32_t *)(&FlexRAM[offset]) = val32;
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flexram_wait();
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}
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offset += 4;
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len -= 4;
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} else if ((lsb == 0 || lsb == 2) && len >= 2) {
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// write aligned 16 bits
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uint16_t val16;
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val16 = *src++;
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val16 |= (*src++ << 8);
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if (*(uint16_t *)(&FlexRAM[offset]) != val16) {
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*(uint16_t *)(&FlexRAM[offset]) = val16;
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flexram_wait();
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}
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offset += 2;
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len -= 2;
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} else {
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// write 8 bits
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uint8_t val8 = *src++;
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if (FlexRAM[offset] != val8) {
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FlexRAM[offset] = val8;
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flexram_wait();
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}
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offset++;
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len--;
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}
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}
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}
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/*
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void do_flash_cmd(volatile uint8_t *fstat)
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{
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*fstat = 0x80;
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while ((*fstat & 0x80) == 0) ; // wait
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}
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00000000 <do_flash_cmd>:
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0: f06f 037f mvn.w r3, #127 ; 0x7f
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4: 7003 strb r3, [r0, #0]
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6: 7803 ldrb r3, [r0, #0]
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8: f013 0f80 tst.w r3, #128 ; 0x80
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c: d0fb beq.n 6 <do_flash_cmd+0x6>
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e: 4770 bx lr
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*/
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#elif defined(KL2x) /* chip selection */
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/* Teensy LC (emulated) */
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#define SYMVAL(sym) (uint32_t)(((uint8_t *)&(sym)) - ((uint8_t *)0))
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extern uint32_t __eeprom_workarea_start__;
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extern uint32_t __eeprom_workarea_end__;
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#define EEPROM_SIZE 128
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static uint32_t flashend = 0;
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void eeprom_initialize(void)
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{
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const uint16_t *p = (uint16_t *)SYMVAL(__eeprom_workarea_start__);
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do {
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if (*p++ == 0xFFFF) {
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flashend = (uint32_t)(p - 2);
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return;
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}
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} while (p < (uint16_t *)SYMVAL(__eeprom_workarea_end__));
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flashend = (uint32_t)((uint16_t *)SYMVAL(__eeprom_workarea_end__) - 1);
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}
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uint8_t eeprom_read_byte(const uint8_t *addr)
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{
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uint32_t offset = (uint32_t)addr;
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const uint16_t *p = (uint16_t *)SYMVAL(__eeprom_workarea_start__);
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const uint16_t *end = (const uint16_t *)((uint32_t)flashend);
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uint16_t val;
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uint8_t data=0xFF;
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if (!end) {
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eeprom_initialize();
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end = (const uint16_t *)((uint32_t)flashend);
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}
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if (offset < EEPROM_SIZE) {
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while (p <= end) {
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val = *p++;
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if ((val & 255) == offset) data = val >> 8;
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}
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}
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return data;
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}
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static void flash_write(const uint16_t *code, uint32_t addr, uint32_t data)
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{
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// with great power comes great responsibility....
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uint32_t stat;
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*(uint32_t *)&(FTFA->FCCOB3) = 0x06000000 | (addr & 0x00FFFFFC);
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*(uint32_t *)&(FTFA->FCCOB7) = data;
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__disable_irq();
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(*((void (*)(volatile uint8_t *))((uint32_t)code | 1)))(&(FTFA->FSTAT));
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__enable_irq();
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stat = FTFA->FSTAT & (FTFA_FSTAT_RDCOLERR|FTFA_FSTAT_ACCERR|FTFA_FSTAT_FPVIOL);
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if (stat) {
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FTFA->FSTAT = stat;
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}
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MCM->PLACR |= MCM_PLACR_CFCC;
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}
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void eeprom_write_byte(uint8_t *addr, uint8_t data)
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{
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uint32_t offset = (uint32_t)addr;
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const uint16_t *p, *end = (const uint16_t *)((uint32_t)flashend);
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uint32_t i, val, flashaddr;
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uint16_t do_flash_cmd[] = {
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0x2380, 0x7003, 0x7803, 0xb25b, 0x2b00, 0xdafb, 0x4770};
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uint8_t buf[EEPROM_SIZE];
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if (offset >= EEPROM_SIZE) return;
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if (!end) {
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eeprom_initialize();
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end = (const uint16_t *)((uint32_t)flashend);
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}
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if (++end < (uint16_t *)SYMVAL(__eeprom_workarea_end__)) {
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val = (data << 8) | offset;
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flashaddr = (uint32_t)end;
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flashend = flashaddr;
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if ((flashaddr & 2) == 0) {
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val |= 0xFFFF0000;
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} else {
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val <<= 16;
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val |= 0x0000FFFF;
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}
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flash_write(do_flash_cmd, flashaddr, val);
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} else {
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for (i=0; i < EEPROM_SIZE; i++) {
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buf[i] = 0xFF;
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}
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for (p = (uint16_t *)SYMVAL(__eeprom_workarea_start__); p < (uint16_t *)SYMVAL(__eeprom_workarea_end__); p++) {
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val = *p;
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if ((val & 255) < EEPROM_SIZE) {
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buf[val & 255] = val >> 8;
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}
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}
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buf[offset] = data;
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for (flashaddr=(uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_start__); flashaddr < (uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_end__); flashaddr += 1024) {
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*(uint32_t *)&(FTFA->FCCOB3) = 0x09000000 | flashaddr;
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__disable_irq();
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(*((void (*)(volatile uint8_t *))((uint32_t)do_flash_cmd | 1)))(&(FTFA->FSTAT));
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__enable_irq();
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val = FTFA->FSTAT & (FTFA_FSTAT_RDCOLERR|FTFA_FSTAT_ACCERR|FTFA_FSTAT_FPVIOL);;
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if (val) FTFA->FSTAT = val;
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MCM->PLACR |= MCM_PLACR_CFCC;
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}
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flashaddr=(uint32_t)(uint16_t *)SYMVAL(__eeprom_workarea_start__);
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for (i=0; i < EEPROM_SIZE; i++) {
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if (buf[i] == 0xFF) continue;
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if ((flashaddr & 2) == 0) {
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val = (buf[i] << 8) | i;
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} else {
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val = val | (buf[i] << 24) | (i << 16);
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flash_write(do_flash_cmd, flashaddr, val);
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}
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flashaddr += 2;
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}
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flashend = flashaddr;
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if ((flashaddr & 2)) {
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val |= 0xFFFF0000;
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flash_write(do_flash_cmd, flashaddr, val);
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}
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}
|
||||
}
|
||||
|
||||
/*
|
||||
void do_flash_cmd(volatile uint8_t *fstat)
|
||||
{
|
||||
*fstat = 0x80;
|
||||
while ((*fstat & 0x80) == 0) ; // wait
|
||||
}
|
||||
00000000 <do_flash_cmd>:
|
||||
0: 2380 movs r3, #128 ; 0x80
|
||||
2: 7003 strb r3, [r0, #0]
|
||||
4: 7803 ldrb r3, [r0, #0]
|
||||
6: b25b sxtb r3, r3
|
||||
8: 2b00 cmp r3, #0
|
||||
a: dafb bge.n 4 <do_flash_cmd+0x4>
|
||||
c: 4770 bx lr
|
||||
*/
|
||||
|
||||
|
||||
uint16_t eeprom_read_word(const uint16_t *addr)
|
||||
{
|
||||
const uint8_t *p = (const uint8_t *)addr;
|
||||
return eeprom_read_byte(p) | (eeprom_read_byte(p+1) << 8);
|
||||
}
|
||||
|
||||
uint32_t eeprom_read_dword(const uint32_t *addr)
|
||||
{
|
||||
const uint8_t *p = (const uint8_t *)addr;
|
||||
return eeprom_read_byte(p) | (eeprom_read_byte(p+1) << 8)
|
||||
| (eeprom_read_byte(p+2) << 16) | (eeprom_read_byte(p+3) << 24);
|
||||
}
|
||||
|
||||
void eeprom_read_block(void *buf, const void *addr, uint32_t len)
|
||||
{
|
||||
const uint8_t *p = (const uint8_t *)addr;
|
||||
uint8_t *dest = (uint8_t *)buf;
|
||||
while (len--) {
|
||||
*dest++ = eeprom_read_byte(p++);
|
||||
}
|
||||
}
|
||||
|
||||
int eeprom_is_ready(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
void eeprom_write_word(uint16_t *addr, uint16_t value)
|
||||
{
|
||||
uint8_t *p = (uint8_t *)addr;
|
||||
eeprom_write_byte(p++, value);
|
||||
eeprom_write_byte(p, value >> 8);
|
||||
}
|
||||
|
||||
void eeprom_write_dword(uint32_t *addr, uint32_t value)
|
||||
{
|
||||
uint8_t *p = (uint8_t *)addr;
|
||||
eeprom_write_byte(p++, value);
|
||||
eeprom_write_byte(p++, value >> 8);
|
||||
eeprom_write_byte(p++, value >> 16);
|
||||
eeprom_write_byte(p, value >> 24);
|
||||
}
|
||||
|
||||
void eeprom_write_block(const void *buf, void *addr, uint32_t len)
|
||||
{
|
||||
uint8_t *p = (uint8_t *)addr;
|
||||
const uint8_t *src = (const uint8_t *)buf;
|
||||
while (len--) {
|
||||
eeprom_write_byte(p++, *src++);
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
#error EEPROM support not implemented for your chip
|
||||
#endif /* chip selection */
|
||||
|
||||
|
||||
/*****************/
|
||||
/* TMK functions */
|
||||
/*****************/
|
||||
|
||||
void eeconfig_init(void)
|
||||
{
|
||||
eeprom_write_word(EECONFIG_MAGIC, EECONFIG_MAGIC_NUMBER);
|
||||
eeprom_write_byte(EECONFIG_DEBUG, 0);
|
||||
eeprom_write_byte(EECONFIG_DEFAULT_LAYER, 0);
|
||||
eeprom_write_byte(EECONFIG_KEYMAP, 0);
|
||||
eeprom_write_byte(EECONFIG_MOUSEKEY_ACCEL, 0);
|
||||
#ifdef BACKLIGHT_ENABLE
|
||||
eeprom_write_byte(EECONFIG_BACKLIGHT, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void eeconfig_enable(void)
|
||||
{
|
||||
eeprom_write_word(EECONFIG_MAGIC, EECONFIG_MAGIC_NUMBER);
|
||||
}
|
||||
|
||||
void eeconfig_disable(void)
|
||||
{
|
||||
eeprom_write_word(EECONFIG_MAGIC, 0xFFFF);
|
||||
}
|
||||
|
||||
bool eeconfig_is_enabled(void)
|
||||
{
|
||||
return (eeprom_read_word(EECONFIG_MAGIC) == EECONFIG_MAGIC_NUMBER);
|
||||
}
|
||||
|
||||
uint8_t eeconfig_read_debug(void) { return eeprom_read_byte(EECONFIG_DEBUG); }
|
||||
void eeconfig_write_debug(uint8_t val) { eeprom_write_byte(EECONFIG_DEBUG, val); }
|
||||
|
||||
uint8_t eeconfig_read_default_layer(void) { return eeprom_read_byte(EECONFIG_DEFAULT_LAYER); }
|
||||
void eeconfig_write_default_layer(uint8_t val) { eeprom_write_byte(EECONFIG_DEFAULT_LAYER, val); }
|
||||
|
||||
uint8_t eeconfig_read_keymap(void) { return eeprom_read_byte(EECONFIG_KEYMAP); }
|
||||
void eeconfig_write_keymap(uint8_t val) { eeprom_write_byte(EECONFIG_KEYMAP, val); }
|
||||
|
||||
#ifdef BACKLIGHT_ENABLE
|
||||
uint8_t eeconfig_read_backlight(void) { return eeprom_read_byte(EECONFIG_BACKLIGHT); }
|
||||
void eeconfig_write_backlight(uint8_t val) { eeprom_write_byte(EECONFIG_BACKLIGHT, val); }
|
||||
#endif
|
||||
@ -18,7 +18,6 @@ SRC += $(COMMON_DIR)/host.c \
|
||||
|
||||
# Option modules
|
||||
ifdef BOOTMAGIC_ENABLE
|
||||
$(error Bootmagic Not Supported)
|
||||
SRC += $(COMMON_DIR)/bootmagic.c
|
||||
SRC += $(COMMON_DIR)/chibios/eeconfig.c
|
||||
OPT_DEFS += -DBOOTMAGIC_ENABLE
|
||||
|
||||
Loading…
Reference in New Issue
Block a user