1
0

ibm4704_usb: Fix interrupt of clock(rising edge)

This commit is contained in:
tmk 2015-05-14 15:38:15 +09:00
parent 6014d1014e
commit 9a2282157f
3 changed files with 27 additions and 30 deletions

View File

@ -51,8 +51,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>.
#define IBM4704_DATA_DDR DDRD #define IBM4704_DATA_DDR DDRD
#define IBM4704_DATA_BIT 0 #define IBM4704_DATA_BIT 0
/* Pin interrupt on rising edge */ /* Pin interrupt on rising edge of clock */
#define IBM4704_INT_INIT() do { EICRA |= ((1<<ISC11)|(0<<ISC10)); } while (0) #define IBM4704_INT_INIT() do { EICRA |= ((1<<ISC11)|(1<<ISC10)); } while (0)
#define IBM4704_INT_ON() do { EIMSK |= (1<<INT1); } while (0) #define IBM4704_INT_ON() do { EIMSK |= (1<<INT1); } while (0)
#define IBM4704_INT_OFF() do { EIMSK &= ~(1<<INT1); } while (0) #define IBM4704_INT_OFF() do { EIMSK &= ~(1<<INT1); } while (0)
#define IBM4704_INT_VECT INT1_vect #define IBM4704_INT_VECT INT1_vect

View File

@ -57,15 +57,15 @@ Keyboard to Host
---------------- ----------------
Data bits are LSB first and Pairty is odd. Clock has around 60us high and 30us low part. Data bits are LSB first and Pairty is odd. Clock has around 60us high and 30us low part.
____ __ __ __ __ __ __ __ __ __ ________ ____ __ __ __ __ __ __ __ __ __ _______
Clock \____/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ Clock \_____/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____ ____
Data ____/ X____X____X____X____X____X____X____X____X____X________ Data ____/ X____X____X____X____X____X____X____X____X____X________
Start 0 1 2 3 4 5 6 7 P Stop Start 0 1 2 3 4 5 6 7 P Stop
Start bit: can be long as 300-350us. Start bit: can be long as 300-350us.
Inhibit: Pull Data line down to inhibit keyboard to send. Inhibit: Pull Data line down to inhibit keyboard to send.
Timing: Host reads bit while Clock is hi. Timing: Host reads bit while Clock is hi.(rising edge)
Stop bit: Keyboard pulls down Data line to lo after 9th clock. Stop bit: Keyboard pulls down Data line to lo after 9th clock.

View File

@ -104,22 +104,6 @@ uint8_t ibm4704_recv_response(void)
return rbuf_dequeue(); return rbuf_dequeue();
} }
/*
Keyboard to Host
----------------
Data bits are LSB first and Parity is odd. Clock has around 60us high and 30us low part.
____ __ __ __ __ __ __ __ __ __ ________
Clock \____/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
____ ____ ____ ____ ____ ____ ____ ____ ____ ____
Data ____/ X____X____X____X____X____X____X____X____X____X________
Start 0 1 2 3 4 5 6 7 P Stop
Start bit: can be long as 300-350us.
Inhibit: Pull Data line down to inhibit keyboard to send.
Timing: Host reads bit while Clock is hi.
Stop bit: Keyboard pulls down Data line to lo after 9th clock.
*/
uint8_t ibm4704_recv(void) uint8_t ibm4704_recv(void)
{ {
if (rbuf_has_data()) { if (rbuf_has_data()) {
@ -129,25 +113,38 @@ uint8_t ibm4704_recv(void)
} }
} }
/*
Keyboard to Host
----------------
Data bits are LSB first and Parity is odd. Clock has around 60us high and 30us low part.
____ __ __ __ __ __ __ __ __ __ _______
Clock \_____/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/
____ ____ ____ ____ ____ ____ ____ ____ ____ ____
Data ____/ X____X____X____X____X____X____X____X____X____X________
Start 0 1 2 3 4 5 6 7 P Stop
Start bit: can be long as 300-350us.
Inhibit: Pull Data line down to inhibit keyboard to send.
Timing: Host reads bit while Clock is hi.(rising edge)
Stop bit: Keyboard pulls down Data line to lo after 9th clock.
*/
ISR(IBM4704_INT_VECT) ISR(IBM4704_INT_VECT)
{ {
static enum { static enum {
INIT, START, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, PARITY, STOP, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, PARITY
} state = INIT; } state = STOP;
// LSB first // LSB first
static uint8_t data = 0; static uint8_t data = 0;
// Odd parity // Odd parity
static uint8_t parity = false; static uint8_t parity = false;
ibm4704_error = 0; ibm4704_error = 0;
// return unless falling edge
if (clock_in()) { goto RETURN; } // why this occurs?
state++; switch (state++) {
switch (state) { case STOP:
case START:
// Data:Low // Data:Low
WAIT(data_hi, 10, state); WAIT(data_lo, 10, state);
break; break;
case BIT0: case BIT0:
case BIT1: case BIT1:
@ -182,7 +179,7 @@ ERROR:
while (ibm4704_send(0xFE)) _delay_ms(1); // resend while (ibm4704_send(0xFE)) _delay_ms(1); // resend
xprintf("R:%02X%02X\n", state, data); xprintf("R:%02X%02X\n", state, data);
DONE: DONE:
state = INIT; state = STOP;
data = 0; data = 0;
parity = false; parity = false;
RETURN: RETURN: