Keyboard firmwares for Atmel AVR and Cortex-M
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ohci_wrapp_RZ_A1.c 54KB

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  1. /* Copyright (c) 2010-2011 mbed.org, MIT License
  2. *
  3. * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
  4. * and associated documentation files (the "Software"), to deal in the Software without
  5. * restriction, including without limitation the rights to use, copy, modify, merge, publish,
  6. * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
  7. * Software is furnished to do so, subject to the following conditions:
  8. *
  9. * The above copyright notice and this permission notice shall be included in all copies or
  10. * substantial portions of the Software.
  11. *
  12. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  13. * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  14. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
  15. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  16. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  17. */
  18. #include <string.h>
  19. #include "cmsis.h"
  20. #include "cmsis_os.h"
  21. #include "ohci_wrapp_RZ_A1.h"
  22. #include "ohci_wrapp_RZ_A1_local.h"
  23. #include "rza_io_regrw.h"
  24. #include "usb_host_setting.h"
  25. /* ------------------ HcControl Register --------------------- */
  26. #define OR_CONTROL_PLE (0x00000004)
  27. #define OR_CONTROL_IE (0x00000008)
  28. #define OR_CONTROL_CLE (0x00000010)
  29. #define OR_CONTROL_BLE (0x00000020)
  30. /* ----------------- HcCommandStatus Register ----------------- */
  31. #define OR_CMD_STATUS_HCR (0x00000001)
  32. #define OR_CMD_STATUS_CLF (0x00000002)
  33. #define OR_CMD_STATUS_BLF (0x00000004)
  34. #define OR_CMD_STATUS_OCR (0x00000008)
  35. /* --------------- HcInterruptStatus Register ----------------- */
  36. #define OR_INTR_STATUS_WDH (0x00000002)
  37. #define OR_INTR_STATUS_RHSC (0x00000040)
  38. /* --------------- HcInterruptEnable Register ----------------- */
  39. #define OR_INTR_ENABLE_WDH (0x00000002)
  40. #define OR_INTR_ENABLE_RHSC (0x00000040)
  41. /* -------------- HcRhPortStatus[1:NDP] Register -------------- */
  42. #define OR_RH_PORT_CSC (0x00010000)
  43. #define OR_RH_PORT_LSDA (0x00000200)
  44. #define OR_RH_PORT_PRS (0x00000010)
  45. #define OR_RH_PORT_POCI (0x00000008)
  46. #define OR_RH_PORT_CCS (0x00000001)
  47. #define ED_FORMAT (0x00008000) /* Format */
  48. #define ED_SKIP (0x00004000) /* Skip this ep in queue */
  49. #define ED_TOGLE_CARRY (0x00000002)
  50. #define ED_HALTED (0x00000001)
  51. #define TD_SETUP (0x00000000) /* Direction of Setup Packet */
  52. #define TD_OUT (0x00080000) /* Direction Out */
  53. #define TD_TOGGLE_0 (0x02000000) /* Toggle 0 */
  54. #define TD_TOGGLE_1 (0x03000000) /* Toggle 1 */
  55. /* -------------- USB Standard Requests -------------- */
  56. #define GET_STATUS (0x00)
  57. #define SET_FEATURE (0x03)
  58. #define SET_ADDRESS (0x05)
  59. #define TD_CTL_MSK_DP (0x00180000)
  60. #define TD_CTL_MSK_T (0x03000000)
  61. #define TD_CTL_MSK_CC (0xF0000000)
  62. #define TD_CTL_MSK_EC (0x0C000000)
  63. #define TD_CTL_SHFT_CC (28)
  64. #define TD_CTL_SHFT_EC (26)
  65. #define TD_CTL_SHFT_T (24)
  66. #define ED_SHFT_TOGLE_CARRY (1)
  67. #define SIG_GEN_LIST_REQ (1)
  68. #if (ISO_TRANS_MAX_NUM > 0)
  69. #define TD_PSW_MSK_CC (0xF000)
  70. #define TD_PSW_SHFT_CC (12)
  71. #define TD_CTL_MSK_FC (0x07000000)
  72. #define TD_CTL_SHFT_FC (24)
  73. #endif
  74. #define CTL_TRANS_TIMEOUT (1000)
  75. #define BLK_TRANS_TIMEOUT (5)
  76. #define TOTAL_SEM_NUM (5 + (2 * INT_TRANS_MAX_NUM) + (2 * ISO_TRANS_MAX_NUM))
  77. #define PORT_LOW_SPEED (0x00000200)
  78. #define PORT_HIGH_SPEED (0x00000400)
  79. #define PORT_NUM (16 + 1) /* num + root(1) */
  80. typedef struct tag_hctd {
  81. uint32_t control; /* Transfer descriptor control */
  82. uint8_t *currBufPtr; /* Physical address of current buffer pointer */
  83. struct tag_hctd *nextTD; /* Physical pointer to next Transfer Descriptor */
  84. uint8_t *bufEnd; /* Physical address of end of buffer */
  85. } hctd_t;
  86. #if (ISO_TRANS_MAX_NUM > 0)
  87. #define PSW_NUM (8)
  88. typedef struct tag_hcisotd {
  89. uint32_t control; /* Transfer descriptor control */
  90. uint8_t *bufferPage0; /* Buffer Page 0 */
  91. struct tag_hcisotd *nextTD; /* Physical pointer to next Transfer Descriptor */
  92. uint8_t *bufEnd; /* Physical address of end of buffer */
  93. uint16_t offsetPSW[PSW_NUM]; /* Offset/PSW */
  94. } hcisotd_t;
  95. #endif
  96. typedef struct tag_hced {
  97. uint32_t control; /* Endpoint descriptor control */
  98. uint32_t tailTD; /* Physical address of tail in Transfer descriptor list */
  99. uint32_t headTD; /* Physcial address of head in Transfer descriptor list */
  100. struct tag_hced *nextED; /* Physical address of next Endpoint descriptor */
  101. } hced_t;
  102. typedef struct tag_hcca {
  103. uint32_t IntTable[32]; /* Interrupt Table */
  104. uint32_t FrameNumber; /* Frame Number */
  105. uint32_t DoneHead; /* Done Head */
  106. volatile uint8_t Reserved[116]; /* Reserved for future use */
  107. volatile uint8_t Unknown[4]; /* Unused */
  108. } hcca_t;
  109. typedef struct tag_usb_ohci_reg {
  110. volatile uint32_t HcRevision;
  111. volatile uint32_t HcControl;
  112. volatile uint32_t HcCommandStatus;
  113. volatile uint32_t HcInterruptStatus;
  114. volatile uint32_t HcInterruptEnable;
  115. volatile uint32_t HcInterruptDisable;
  116. volatile uint32_t HcHCCA;
  117. volatile uint32_t HcPeriodCurrentED;
  118. volatile uint32_t HcControlHeadED;
  119. volatile uint32_t HcControlCurrentED;
  120. volatile uint32_t HcBulkHeadED;
  121. volatile uint32_t HcBulkCurrentED;
  122. volatile uint32_t HcDoneHead;
  123. volatile uint32_t HcFmInterval;
  124. volatile uint32_t HcFmRemaining;
  125. volatile uint32_t HcFmNumber;
  126. volatile uint32_t HcPeriodicStart;
  127. volatile uint32_t HcLSThreshold;
  128. volatile uint32_t HcRhDescriptorA;
  129. volatile uint32_t HcRhDescriptorB;
  130. volatile uint32_t HcRhStatus;
  131. volatile uint32_t HcRhPortStatus1;
  132. } usb_ohci_reg_t;
  133. typedef struct tag_genelal_ed {
  134. osThreadId tskid;
  135. osSemaphoreId semid_wait;
  136. osSemaphoreId semid_list;
  137. void *p_curr_td; /* pointer of hctd_t or hcisotd_t */
  138. hced_t *p_curr_ed;
  139. uint32_t pipe_no;
  140. uint32_t trans_wait;
  141. uint32_t cycle_time;
  142. uint8_t *p_start_buf;
  143. #if (ISO_TRANS_MAX_NUM > 0)
  144. uint32_t psw_idx;
  145. #endif
  146. } genelal_ed_t;
  147. typedef struct tag_tdinfo {
  148. uint32_t count;
  149. uint32_t direction;
  150. uint32_t msp;
  151. uint16_t devadr;
  152. uint16_t speed; /* 1:Speed = Low */
  153. uint8_t endpoint_no;
  154. } tdinfo_t;
  155. typedef struct tag_split_trans {
  156. uint16_t root_devadr;
  157. uint16_t get_port;
  158. uint16_t port_speed;
  159. uint16_t reset_port;
  160. uint32_t seq_cnt;
  161. uint32_t port_sts_bits[PORT_NUM];
  162. } split_trans_t;
  163. static void callback_task(void const * argument);
  164. static void control_ed_task(void const * argument);
  165. static void bulk_ed_task(void const * argument);
  166. static void int_ed_task(void const * argument);
  167. static int32_t int_trans_doing(hced_t *p_ed, uint32_t index);
  168. static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed);
  169. static void chk_genelal_td_done(genelal_ed_t *p_g_ed);
  170. static void chk_split_trans_setting(genelal_ed_t *p_g_ed);
  171. static void set_split_trans_setting(void);
  172. static void control_trans(genelal_ed_t *p_g_ed);
  173. static void bulk_trans(genelal_ed_t *p_g_ed);
  174. static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index);
  175. static uint32_t chk_cycle(hced_t *p_ed);
  176. static void int_trans(genelal_ed_t *p_g_ed);
  177. static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info);
  178. static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed);
  179. #if (ISO_TRANS_MAX_NUM > 0)
  180. static void iso_ed_task(void const * argument);
  181. static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index);
  182. static void chk_iso_td_done(genelal_ed_t *p_g_ed);
  183. static int32_t chk_iso_ed(genelal_ed_t *p_g_ed);
  184. static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index);
  185. static uint32_t iso_chk_starting_frame(genelal_ed_t *p_g_ed);
  186. static void iso_trans(genelal_ed_t *p_g_ed);
  187. #endif
  188. static void connect_check(void);
  189. extern USB_HOST_CFG_PIPETBL_t usb_host_blk_ep_tbl1[];
  190. extern USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[];
  191. #if (ISO_TRANS_MAX_NUM > 0)
  192. extern USB_HOST_CFG_PIPETBL_t usb_host_iso_ep_tbl1[];
  193. #endif
  194. static usb_ohci_reg_t usb_reg;
  195. static usb_ohci_reg_t *p_usb_reg = &usb_reg;
  196. static usbisr_fnc_t *p_usbisr_cb = NULL;
  197. static osSemaphoreId semid_cb = NULL;
  198. static uint32_t connect_change = 0xFFFFFFFF;
  199. static uint32_t init_end = 0;
  200. static genelal_ed_t ctl_ed;
  201. static genelal_ed_t blk_ed;
  202. static genelal_ed_t int_ed[INT_TRANS_MAX_NUM];
  203. static split_trans_t split_ctl;
  204. #if (ISO_TRANS_MAX_NUM > 0)
  205. static genelal_ed_t iso_ed[ISO_TRANS_MAX_NUM];
  206. #endif
  207. osSemaphoreDef(ohciwrapp_sem_01);
  208. osSemaphoreDef(ohciwrapp_sem_02);
  209. osSemaphoreDef(ohciwrapp_sem_03);
  210. osSemaphoreDef(ohciwrapp_sem_04);
  211. osSemaphoreDef(ohciwrapp_sem_05);
  212. osSemaphoreDef(ohciwrapp_sem_06);
  213. osSemaphoreDef(ohciwrapp_sem_07);
  214. #if (INT_TRANS_MAX_NUM >= 2)
  215. osSemaphoreDef(ohciwrapp_sem_08);
  216. osSemaphoreDef(ohciwrapp_sem_09);
  217. #endif
  218. #if (INT_TRANS_MAX_NUM >= 3)
  219. osSemaphoreDef(ohciwrapp_sem_10);
  220. osSemaphoreDef(ohciwrapp_sem_11);
  221. #endif
  222. #if (INT_TRANS_MAX_NUM >= 4)
  223. osSemaphoreDef(ohciwrapp_sem_12);
  224. osSemaphoreDef(ohciwrapp_sem_13);
  225. #endif
  226. #if (ISO_TRANS_MAX_NUM >= 1)
  227. osSemaphoreDef(ohciwrapp_sem_14);
  228. osSemaphoreDef(ohciwrapp_sem_15);
  229. #endif
  230. #if (ISO_TRANS_MAX_NUM >= 2)
  231. osSemaphoreDef(ohciwrapp_sem_16);
  232. osSemaphoreDef(ohciwrapp_sem_17);
  233. #endif
  234. osThreadDef(callback_task, osPriorityHigh, 512);
  235. osThreadDef(control_ed_task, osPriorityNormal, 512);
  236. osThreadDef(bulk_ed_task, osPriorityNormal, 512);
  237. static void int_ed_task_1(void const * argument) {
  238. int_ed_task(argument);
  239. }
  240. osThreadDef(int_ed_task_1, osPriorityNormal, 512);
  241. #if (INT_TRANS_MAX_NUM >= 2)
  242. static void int_ed_task_2(void const * argument) {
  243. int_ed_task(argument);
  244. }
  245. osThreadDef(int_ed_task_2, osPriorityNormal, 512);
  246. #endif
  247. #if (INT_TRANS_MAX_NUM >= 3)
  248. static void int_ed_task_3(void const * argument) {
  249. int_ed_task(argument);
  250. }
  251. osThreadDef(int_ed_task_3, osPriorityNormal, 512);
  252. #endif
  253. #if (INT_TRANS_MAX_NUM >= 4)
  254. static void int_ed_task_4(void const * argument) {
  255. int_ed_task(argument);
  256. }
  257. osThreadDef(int_ed_task_4, osPriorityNormal, 512);
  258. #endif
  259. #if (ISO_TRANS_MAX_NUM >= 1)
  260. static void iso_ed_task_1(void const * argument) {
  261. iso_ed_task(argument);
  262. }
  263. osThreadDef(iso_ed_task_1, osPriorityNormal, 512);
  264. #endif
  265. #if (ISO_TRANS_MAX_NUM >= 2)
  266. static void iso_ed_task_2(void const * argument) {
  267. iso_ed_task(argument);
  268. }
  269. osThreadDef(iso_ed_task_2, osPriorityNormal, 512);
  270. #endif
  271. void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc) {
  272. static const osSemaphoreDef_t * const sem_def_tbl[TOTAL_SEM_NUM] = {
  273. osSemaphore(ohciwrapp_sem_01), osSemaphore(ohciwrapp_sem_02), osSemaphore(ohciwrapp_sem_03)
  274. , osSemaphore(ohciwrapp_sem_04), osSemaphore(ohciwrapp_sem_05), osSemaphore(ohciwrapp_sem_06)
  275. , osSemaphore(ohciwrapp_sem_07)
  276. #if (INT_TRANS_MAX_NUM >= 2)
  277. , osSemaphore(ohciwrapp_sem_08), osSemaphore(ohciwrapp_sem_09)
  278. #endif
  279. #if (INT_TRANS_MAX_NUM >= 3)
  280. , osSemaphore(ohciwrapp_sem_10), osSemaphore(ohciwrapp_sem_11)
  281. #endif
  282. #if (INT_TRANS_MAX_NUM >= 4)
  283. , osSemaphore(ohciwrapp_sem_12), osSemaphore(ohciwrapp_sem_13)
  284. #endif
  285. #if (ISO_TRANS_MAX_NUM >= 1)
  286. , osSemaphore(ohciwrapp_sem_14), osSemaphore(ohciwrapp_sem_15)
  287. #endif
  288. #if (ISO_TRANS_MAX_NUM >= 2)
  289. , osSemaphore(ohciwrapp_sem_16), osSemaphore(ohciwrapp_sem_17)
  290. #endif
  291. };
  292. static const osThreadDef_t * const int_tsk_def_tbl[INT_TRANS_MAX_NUM] = {
  293. osThread(int_ed_task_1)
  294. #if (INT_TRANS_MAX_NUM >= 2)
  295. , osThread(int_ed_task_2)
  296. #endif
  297. #if (INT_TRANS_MAX_NUM >= 3)
  298. , osThread(int_ed_task_3)
  299. #endif
  300. #if (INT_TRANS_MAX_NUM >= 4)
  301. , osThread(int_ed_task_4)
  302. #endif
  303. };
  304. #if (ISO_TRANS_MAX_NUM > 0)
  305. static const osThreadDef_t * const iso_tsk_def_tbl[ISO_TRANS_MAX_NUM] = {
  306. osThread(iso_ed_task_1)
  307. #if (ISO_TRANS_MAX_NUM >= 2)
  308. , osThread(iso_ed_task_2)
  309. #endif
  310. };
  311. #endif
  312. uint32_t cnt;
  313. uint32_t index = 0;
  314. /* Disables interrupt for usb */
  315. GIC_DisableIRQ(USBIXUSBIX);
  316. #if (USB_HOST_CH == 0)
  317. /* P4_1(USB0_EN) */
  318. GPIOP4 &= ~0x0002; /* Outputs low level */
  319. GPIOPMC4 &= ~0x0002; /* Port mode */
  320. GPIOPM4 &= ~0x0002; /* Output mode */
  321. #endif
  322. p_usbisr_cb = p_usbisr_fnc;
  323. #if (USB_HOST_HISPEED == 0)
  324. g_usbx_host_SupportUsbDeviceSpeed = USB_HOST_FULL_SPEED;
  325. #else
  326. g_usbx_host_SupportUsbDeviceSpeed = USB_HOST_HIGH_SPEED;
  327. #endif
  328. p_usb_reg->HcRevision = 0x00000010;
  329. p_usb_reg->HcControl = 0x00000000;
  330. p_usb_reg->HcCommandStatus = 0x00000000;
  331. p_usb_reg->HcInterruptStatus = 0x00000000;
  332. p_usb_reg->HcInterruptEnable = 0x00000000;
  333. p_usb_reg->HcInterruptDisable = 0x00000000;
  334. p_usb_reg->HcHCCA = 0x00000000;
  335. p_usb_reg->HcPeriodCurrentED = 0x00000000;
  336. p_usb_reg->HcControlHeadED = 0x00000000;
  337. p_usb_reg->HcControlCurrentED = 0x00000000;
  338. p_usb_reg->HcBulkHeadED = 0x00000000;
  339. p_usb_reg->HcBulkCurrentED = 0x00000000;
  340. p_usb_reg->HcDoneHead = 0x00000000;
  341. p_usb_reg->HcFmInterval = 0x00002EDF;
  342. p_usb_reg->HcFmRemaining = 0x00002EDF;
  343. p_usb_reg->HcFmNumber = 0x00000000;
  344. p_usb_reg->HcPeriodicStart = 0x00000000;
  345. p_usb_reg->HcLSThreshold = 0x00000628;
  346. p_usb_reg->HcRhDescriptorA = 0xFF000901;
  347. p_usb_reg->HcRhDescriptorB = 0x00020000;
  348. p_usb_reg->HcRhStatus = 0x00000000;
  349. p_usb_reg->HcRhPortStatus1 = 0x00000000;
  350. #if (USB_HOST_CH == 0)
  351. GPIOP4 |= 0x0002; /* P4_1 Outputs high level */
  352. osDelay(5);
  353. GPIOP4 &= ~0x0002; /* P4_1 Outputs low level */
  354. osDelay(10);
  355. #else
  356. osDelay(15);
  357. #endif
  358. if (init_end == 0) {
  359. (void)memset(&ctl_ed, 0, sizeof(ctl_ed));
  360. (void)memset(&blk_ed, 0, sizeof(blk_ed));
  361. (void)memset(&int_ed[0], 0, sizeof(int_ed));
  362. #if (ISO_TRANS_MAX_NUM > 0)
  363. (void)memset(&iso_ed[0], 0, sizeof(iso_ed));
  364. #endif
  365. /* callback */
  366. semid_cb = osSemaphoreCreate(sem_def_tbl[index], 0);
  367. index++;
  368. (void)osThreadCreate(osThread(callback_task), 0);
  369. /* control transfer */
  370. ctl_ed.semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
  371. index++;
  372. ctl_ed.semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
  373. index++;
  374. ctl_ed.tskid = osThreadCreate(osThread(control_ed_task), 0);
  375. /* bulk transfer */
  376. blk_ed.semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
  377. index++;
  378. blk_ed.semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
  379. index++;
  380. blk_ed.tskid = osThreadCreate(osThread(bulk_ed_task), 0);
  381. /* interrupt transfer */
  382. for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
  383. int_ed[cnt].semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
  384. index++;
  385. int_ed[cnt].semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
  386. index++;
  387. int_ed[cnt].tskid = osThreadCreate(int_tsk_def_tbl[cnt], (void *)cnt);
  388. }
  389. #if (ISO_TRANS_MAX_NUM > 0)
  390. /* isochronous transfer */
  391. for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
  392. iso_ed[cnt].semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
  393. index++;
  394. iso_ed[cnt].semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
  395. index++;
  396. iso_ed[cnt].tskid = osThreadCreate(iso_tsk_def_tbl[cnt], (void *)cnt);
  397. }
  398. #endif
  399. init_end = 1;
  400. }
  401. }
  402. uint32_t ohciwrapp_reg_r(uint32_t reg_ofs) {
  403. if (init_end == 0) {
  404. return 0;
  405. }
  406. return *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs);
  407. }
  408. void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data) {
  409. uint32_t cnt;
  410. uint32_t last_data;
  411. hcca_t *p_hcca;
  412. if (init_end == 0) {
  413. return;
  414. }
  415. switch (reg_ofs) {
  416. case OHCI_REG_CONTROL:
  417. last_data = p_usb_reg->HcControl;
  418. p_usb_reg->HcControl = (set_data & 0x000007FF);
  419. if ((last_data & OR_CONTROL_CLE) != (set_data & OR_CONTROL_CLE)) {
  420. /* change CLE */
  421. if ((set_data & OR_CONTROL_CLE) != 0) {
  422. (void)osSemaphoreRelease(ctl_ed.semid_list);
  423. } else {
  424. if (ctl_ed.trans_wait == 1) {
  425. ctl_ed.trans_wait = 0;
  426. (void)osSemaphoreRelease(ctl_ed.semid_wait);
  427. }
  428. (void)osSemaphoreWait(ctl_ed.semid_list, osWaitForever);
  429. }
  430. }
  431. if ((last_data & OR_CONTROL_BLE) != (set_data & OR_CONTROL_BLE)) {
  432. /* change BLE */
  433. if ((set_data & OR_CONTROL_BLE) != 0) {
  434. (void)osSemaphoreRelease(blk_ed.semid_list);
  435. } else {
  436. if (blk_ed.trans_wait == 1) {
  437. blk_ed.trans_wait = 0;
  438. (void)osSemaphoreRelease(blk_ed.semid_wait);
  439. }
  440. (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever);
  441. }
  442. }
  443. #if (ISO_TRANS_MAX_NUM > 0)
  444. if ((last_data & OR_CONTROL_IE) != (set_data & OR_CONTROL_IE)) {
  445. /* change IE */
  446. for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
  447. if ((set_data & OR_CONTROL_IE) != 0) {
  448. (void)osSemaphoreRelease(iso_ed[cnt].semid_list);
  449. } else {
  450. if (iso_ed[cnt].trans_wait == 1) {
  451. iso_ed[cnt].trans_wait = 0;
  452. (void)osSemaphoreRelease(iso_ed[cnt].semid_wait);
  453. }
  454. (void)osSemaphoreWait(iso_ed[cnt].semid_list, osWaitForever);
  455. }
  456. }
  457. }
  458. #endif
  459. if ((last_data & OR_CONTROL_PLE) != (set_data & OR_CONTROL_PLE)) {
  460. /* change PLE */
  461. for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
  462. if ((set_data & OR_CONTROL_PLE) != 0) {
  463. (void)osSemaphoreRelease(int_ed[cnt].semid_list);
  464. } else {
  465. if (int_ed[cnt].trans_wait == 1) {
  466. int_ed[cnt].trans_wait = 0;
  467. (void)osSemaphoreRelease(int_ed[cnt].semid_wait);
  468. }
  469. (void)osSemaphoreWait(int_ed[cnt].semid_list, osWaitForever);
  470. }
  471. }
  472. }
  473. break;
  474. case OHCI_REG_COMMANDSTATUS:
  475. if ((set_data & OR_CMD_STATUS_HCR) != 0) { /* HostController Reset */
  476. p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_HCR;
  477. if (usbx_api_host_init(16, g_usbx_host_SupportUsbDeviceSpeed, USBHCLOCK_X1_48MHZ) == USB_HOST_ATTACH) {
  478. ohciwrapp_loc_Connect(1);
  479. }
  480. p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_HCR;
  481. }
  482. if ((set_data & OR_CMD_STATUS_CLF) != 0) {
  483. p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF;
  484. osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ);
  485. }
  486. if ((set_data & OR_CMD_STATUS_BLF) != 0) {
  487. p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF;
  488. osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ);
  489. }
  490. if ((set_data & OR_CMD_STATUS_OCR) != 0) {
  491. p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_OCR;
  492. } else {
  493. p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_OCR;
  494. }
  495. break;
  496. case OHCI_REG_INTERRUPTSTATUS:
  497. if (((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) != 0)
  498. && ((set_data & OR_INTR_STATUS_WDH) != 0)) {
  499. if (p_usb_reg->HcDoneHead != 0x00000000) {
  500. p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
  501. p_hcca->DoneHead = p_usb_reg->HcDoneHead;
  502. p_usb_reg->HcDoneHead = 0x00000000;
  503. p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
  504. (void)osSemaphoreRelease(semid_cb);
  505. } else {
  506. p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_WDH;
  507. }
  508. }
  509. if ((set_data & OR_INTR_STATUS_RHSC) != 0) {
  510. p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_RHSC;
  511. }
  512. break;
  513. case OHCI_REG_INTERRUPTENABLE:
  514. case OHCI_REG_INTERRUPTDISABLE:
  515. case OHCI_REG_HCCA:
  516. case OHCI_REG_CONTROLHEADED:
  517. case OHCI_REG_CONTROLCURRENTED:
  518. case OHCI_REG_BULKHEADED:
  519. case OHCI_REG_BULKCURRENTED:
  520. case OHCI_REG_FMINTERVAL:
  521. case OHCI_REG_FMREMAINING:
  522. case OHCI_REG_PERIODICSTART:
  523. case OHCI_REG_LSTHRESHOLD:
  524. case OHCI_REG_RHDESCRIPTORA:
  525. case OHCI_REG_RHDESCRIPTORB:
  526. case OHCI_REG_RHSTATUS:
  527. *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs) = set_data;
  528. break;
  529. case OHCI_REG_RHPORTSTATUS1:
  530. p_usb_reg->HcRhPortStatus1 &= ~(set_data & 0xFFFF0000);
  531. if ((set_data & OR_RH_PORT_PRS) != 0) { /* Set Port Reset */
  532. p_usb_reg->HcRhPortStatus1 |= OR_RH_PORT_PRS;
  533. usbx_host_UsbBusReset();
  534. p_usb_reg->HcRhPortStatus1 &= ~OR_RH_PORT_PRS;
  535. }
  536. break;
  537. case OHCI_REG_REVISION:
  538. case OHCI_REG_PERIODCURRENTED:
  539. case OHCI_REG_DONEHEADED:
  540. case OHCI_REG_FMNUMBER:
  541. default:
  542. /* Do Nothing */
  543. break;
  544. }
  545. }
  546. static void callback_task(void const * argument) {
  547. usbisr_fnc_t *p_wk_cb = p_usbisr_cb;
  548. if (p_wk_cb == NULL) {
  549. return;
  550. }
  551. while (1) {
  552. osSemaphoreWait(semid_cb, osWaitForever);
  553. if (connect_change != 0xFFFFFFFF) {
  554. connect_change = 0xFFFFFFFF;
  555. connect_check();
  556. }
  557. p_wk_cb();
  558. }
  559. }
  560. static void control_ed_task(void const * argument) {
  561. while (1) {
  562. osSignalWait(SIG_GEN_LIST_REQ, osWaitForever);
  563. (void)osSemaphoreWait(ctl_ed.semid_list, osWaitForever);
  564. while ((p_usb_reg->HcControl & OR_CONTROL_CLE) != 0) {
  565. if ((p_usb_reg->HcControlCurrentED == 0)
  566. && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0)) {
  567. p_usb_reg->HcControlCurrentED = p_usb_reg->HcControlHeadED;
  568. p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_CLF;
  569. }
  570. if (p_usb_reg->HcControlCurrentED != 0) {
  571. ctl_ed.p_curr_ed = (hced_t *)p_usb_reg->HcControlCurrentED;
  572. if (chk_genelal_ed(&ctl_ed) != 0) {
  573. control_trans(&ctl_ed);
  574. p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF;
  575. }
  576. p_usb_reg->HcControlCurrentED = (uint32_t)ctl_ed.p_curr_ed->nextED;
  577. } else {
  578. break;
  579. }
  580. }
  581. if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0) {
  582. osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ);
  583. }
  584. (void)osSemaphoreRelease(ctl_ed.semid_list);
  585. }
  586. }
  587. static void bulk_ed_task(void const * argument) {
  588. while (1) {
  589. osSignalWait(SIG_GEN_LIST_REQ, osWaitForever);
  590. (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever);
  591. while ((p_usb_reg->HcControl & OR_CONTROL_BLE) != 0) {
  592. if ((p_usb_reg->HcBulkCurrentED == 0)
  593. && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0)) {
  594. p_usb_reg->HcBulkCurrentED = p_usb_reg->HcBulkHeadED;
  595. p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_BLF;
  596. }
  597. if (p_usb_reg->HcBulkCurrentED != 0) {
  598. blk_ed.p_curr_ed = (hced_t *)p_usb_reg->HcBulkCurrentED;
  599. if (chk_genelal_ed(&blk_ed) != 0) {
  600. bulk_trans(&blk_ed);
  601. p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF;
  602. }
  603. p_usb_reg->HcBulkCurrentED = (uint32_t)blk_ed.p_curr_ed->nextED;
  604. } else {
  605. break;
  606. }
  607. }
  608. if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0) {
  609. osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ);
  610. }
  611. (void)osSemaphoreRelease(blk_ed.semid_list);
  612. }
  613. }
  614. static void int_ed_task(void const * argument) {
  615. genelal_ed_t *p_int_ed = &int_ed[(uint32_t)argument];
  616. uint32_t cnt;
  617. uint32_t wait_cnt = 0;
  618. hcca_t *p_hcca;
  619. hced_t *p_ed;
  620. while (1) {
  621. (void)osSemaphoreWait(p_int_ed->semid_list, osWaitForever);
  622. if (p_int_ed->p_curr_ed == NULL) {
  623. for (cnt = 0; (cnt < 32) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0)
  624. && (p_int_ed->p_curr_ed == NULL); cnt++) {
  625. p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
  626. p_ed = (hced_t *)p_hcca->IntTable[cnt];
  627. while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0)
  628. && (p_int_ed->p_curr_ed == NULL)) {
  629. if (int_trans_doing(p_ed, (uint32_t)argument) == 0) {
  630. p_int_ed->p_curr_ed = p_ed;
  631. if (chk_genelal_ed(p_int_ed) != 0) {
  632. int_trans_setting(p_int_ed, (uint32_t)argument);
  633. } else {
  634. p_int_ed->p_curr_ed = NULL;
  635. }
  636. }
  637. p_ed = p_ed->nextED;
  638. }
  639. }
  640. }
  641. if (p_int_ed->p_curr_ed != NULL) {
  642. while ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0) {
  643. if (chk_genelal_ed(p_int_ed) != 0) {
  644. int_trans(p_int_ed);
  645. (void)osSemaphoreWait(p_int_ed->semid_wait, osWaitForever);
  646. usbx_host_stop_transfer(p_int_ed->pipe_no);
  647. wait_cnt = p_int_ed->cycle_time;
  648. } else {
  649. if (wait_cnt > 0) {
  650. wait_cnt--;
  651. } else {
  652. p_int_ed->p_curr_ed = NULL;
  653. }
  654. break;
  655. }
  656. }
  657. }
  658. (void)osSemaphoreRelease(p_int_ed->semid_list);
  659. if (p_int_ed->p_curr_ed == NULL) {
  660. osDelay(10);
  661. } else {
  662. osDelay(1);
  663. }
  664. }
  665. }
  666. static int32_t int_trans_doing(hced_t *p_ed, uint32_t index) {
  667. uint32_t cnt;
  668. int32_t ret = 0;
  669. for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
  670. if ((index != cnt) && (int_ed[cnt].p_curr_ed == p_ed)) {
  671. ret = 1;
  672. }
  673. }
  674. return ret;
  675. }
  676. static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed){
  677. int32_t ret = 0;
  678. hced_t *p_ed = p_g_ed->p_curr_ed;
  679. if (((p_ed->control & ED_SKIP) != 0)
  680. || ((p_ed->control & ED_FORMAT) != 0)
  681. || ((p_ed->headTD & ED_HALTED) != 0)
  682. || ((p_ed->tailTD & 0xFFFFFFF0) == (p_ed->headTD & 0xFFFFFFF0))) {
  683. /* Do Nothing */
  684. } else if ((p_ed->control & 0x0000007F) > 10) {
  685. p_ed->headTD |= ED_HALTED;
  686. } else {
  687. p_g_ed->p_curr_td = (void *)(p_ed->headTD & 0xFFFFFFF0);
  688. if (p_g_ed->p_curr_td == NULL) {
  689. p_ed->headTD |= ED_HALTED;
  690. } else {
  691. hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
  692. p_g_ed->p_start_buf = p_td->currBufPtr;
  693. ret = 1;
  694. }
  695. }
  696. return ret;
  697. }
  698. static void chk_genelal_td_done(genelal_ed_t *p_g_ed) {
  699. hcca_t *p_hcca;
  700. hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
  701. uint32_t ConditionCode = RZA_IO_RegRead_32(&p_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
  702. if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) {
  703. p_g_ed->p_curr_ed->headTD = ((uint32_t)p_td->nextTD & 0xFFFFFFF0)
  704. | (p_g_ed->p_curr_ed->headTD & 0x0000000F);
  705. p_td->nextTD = (hctd_t *)p_usb_reg->HcDoneHead;
  706. p_usb_reg->HcDoneHead = (uint32_t)p_g_ed->p_curr_td;
  707. if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) {
  708. p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
  709. p_hcca->DoneHead = p_usb_reg->HcDoneHead;
  710. p_usb_reg->HcDoneHead = 0x00000000;
  711. p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
  712. (void)osSemaphoreRelease(semid_cb);
  713. }
  714. }
  715. }
  716. static void chk_split_trans_setting(genelal_ed_t *p_g_ed) {
  717. uint8_t *p_buf;
  718. tdinfo_t td_info;
  719. hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
  720. /* Hi-Speed mode only */
  721. if (g_usbx_host_UsbDeviceSpeed != USB_HOST_HIGH_SPEED) {
  722. return;
  723. }
  724. if (RZA_IO_RegRead_32(&p_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC) != TD_CC_NOERROR) {
  725. return;
  726. }
  727. get_td_info(p_g_ed, &td_info);
  728. p_buf = p_g_ed->p_start_buf;
  729. if (td_info.direction == 0) {
  730. uint8_t bRequest = p_buf[1];
  731. uint16_t wValue = (p_buf[3] << 8) + p_buf[2];
  732. uint16_t wIndx = (p_buf[5] << 8) + p_buf[4];
  733. uint16_t devadd;
  734. if ((td_info.devadr == 0) && (bRequest == SET_ADDRESS)) {
  735. /* SET_ADDRESS */
  736. usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
  737. usbx_host_set_devadd(wValue, &devadd);
  738. if (split_ctl.root_devadr == 0) {
  739. split_ctl.root_devadr = wValue; /* New Address */
  740. }
  741. } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == SET_FEATURE)
  742. && (wValue == 0x0004) && (split_ctl.root_devadr != 0)) {
  743. /* SET_FEATURE PORT_RESET */
  744. split_ctl.reset_port = (wIndx & 0x00FF);
  745. } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == GET_STATUS)) {
  746. /* GET_STATUS */
  747. split_ctl.get_port = wIndx;
  748. split_ctl.seq_cnt = 1;
  749. } else {
  750. /* Do Nothing */
  751. }
  752. } else if (td_info.direction == 2) {
  753. if ((td_info.devadr == split_ctl.root_devadr) && (split_ctl.seq_cnt == 1)) {
  754. if (split_ctl.get_port < PORT_NUM) {
  755. split_ctl.port_sts_bits[split_ctl.get_port] = (p_buf[1] << 8) + p_buf[0];
  756. }
  757. split_ctl.seq_cnt = 0;
  758. }
  759. } else {
  760. /* Do Nothing */
  761. }
  762. }
  763. static void set_split_trans_setting(void) {
  764. uint16_t port_speed;
  765. uint16_t devadd;
  766. if ((split_ctl.root_devadr != 0) && (split_ctl.reset_port != 0) && (split_ctl.reset_port < PORT_NUM)) {
  767. usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
  768. RZA_IO_RegWrite_16(&devadd, split_ctl.root_devadr, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB);
  769. RZA_IO_RegWrite_16(&devadd, split_ctl.reset_port, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT);
  770. if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_HIGH_SPEED) != 0) {
  771. port_speed = USB_HOST_HIGH_SPEED;
  772. } else if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_LOW_SPEED) != 0) {
  773. port_speed = USB_HOST_LOW_SPEED;
  774. } else {
  775. port_speed = USB_HOST_FULL_SPEED;
  776. }
  777. RZA_IO_RegWrite_16(&devadd, port_speed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
  778. usbx_host_set_devadd(USB_HOST_DEVICE_0, &devadd);
  779. split_ctl.reset_port = 0;
  780. }
  781. }
  782. static void control_trans(genelal_ed_t *p_g_ed) {
  783. hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
  784. tdinfo_t td_info;
  785. uint16_t devadd;
  786. get_td_info(p_g_ed, &td_info);
  787. if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
  788. if (td_info.devadr == 0) {
  789. set_split_trans_setting();
  790. }
  791. } else {
  792. /* When a non-Hi-Speed, the communication speed is determined from the TD. */
  793. usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
  794. if (td_info.speed == 1) {
  795. RZA_IO_RegWrite_16(&devadd, USB_HOST_LOW_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
  796. } else {
  797. RZA_IO_RegWrite_16(&devadd, USB_HOST_FULL_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
  798. }
  799. usbx_host_set_devadd(td_info.devadr, &devadd);
  800. }
  801. USB20X.DCPMAXP = (td_info.devadr << 12) + td_info.msp;
  802. if (td_info.direction == 0) {
  803. g_usbx_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
  804. } else if (td_info.count != 0) {
  805. g_usbx_host_CmdStage = (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE);
  806. } else {
  807. g_usbx_host_CmdStage = (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE);
  808. }
  809. g_usbx_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
  810. p_g_ed->pipe_no = USB_HOST_PIPE0;
  811. p_g_ed->trans_wait = 1;
  812. if (td_info.direction == 0) {
  813. uint16_t Req = (p_td->currBufPtr[1] << 8) + p_td->currBufPtr[0];
  814. uint16_t Val = (p_td->currBufPtr[3] << 8) + p_td->currBufPtr[2];
  815. uint16_t Indx = (p_td->currBufPtr[5] << 8) + p_td->currBufPtr[4];
  816. uint16_t Len = (p_td->currBufPtr[7] << 8) + p_td->currBufPtr[6];
  817. g_usbx_host_data_pointer[USB_HOST_PIPE0] = p_td->bufEnd;
  818. usbx_host_SetupStage(Req, Val, Indx, Len);
  819. } else if (td_info.direction == 1) {
  820. usbx_host_CtrlWriteStart(td_info.count, p_td->currBufPtr);
  821. } else {
  822. usbx_host_CtrlReadStart(td_info.count, p_td->currBufPtr);
  823. }
  824. (void)osSemaphoreWait(p_g_ed->semid_wait, CTL_TRANS_TIMEOUT);
  825. if (p_g_ed->trans_wait == 1) {
  826. p_g_ed->trans_wait = 0;
  827. RZA_IO_RegWrite_32(&p_td->control, TD_CC_DEVICENOTRESPONDING, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
  828. }
  829. g_usbx_host_CmdStage &= (~USB_HOST_CMD_FIELD);
  830. g_usbx_host_CmdStage |= USB_HOST_CMD_IDLE;
  831. g_usbx_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
  832. }
  833. static void bulk_trans(genelal_ed_t *p_g_ed) {
  834. hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
  835. hced_t *p_ed = p_g_ed->p_curr_ed;
  836. tdinfo_t td_info;
  837. USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_blk_ep_tbl1[0];
  838. uint8_t wk_table[6];
  839. get_td_info(p_g_ed, &td_info);
  840. wk_table[0] = 0;
  841. wk_table[1] = USB_HOST_ENDPOINT_DESC;
  842. wk_table[2] = td_info.endpoint_no;
  843. if (td_info.direction == 2) {
  844. wk_table[2] |= USB_HOST_EP_IN;
  845. }
  846. wk_table[3] = USB_HOST_EP_BULK;
  847. wk_table[4] = (uint8_t)td_info.msp;
  848. wk_table[5] = (uint8_t)(td_info.msp >> 8);
  849. p_g_ed->pipe_no = user_table->pipe_number;
  850. usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
  851. set_togle(p_g_ed->pipe_no, p_td, p_ed);
  852. p_g_ed->trans_wait = 1;
  853. if (td_info.direction == 1) {
  854. usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
  855. } else {
  856. usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
  857. }
  858. (void)osSemaphoreWait(p_g_ed->semid_wait, BLK_TRANS_TIMEOUT);
  859. usbx_host_stop_transfer(p_g_ed->pipe_no);
  860. }
  861. static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
  862. hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
  863. hced_t *p_ed = p_g_ed->p_curr_ed;
  864. tdinfo_t td_info;
  865. USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_int_ep_tbl1[index];
  866. uint8_t wk_table[6];
  867. uint32_t cycle_time;
  868. uint16_t devadd;
  869. get_td_info(p_g_ed, &td_info);
  870. wk_table[0] = 0;
  871. wk_table[1] = USB_HOST_ENDPOINT_DESC;
  872. wk_table[2] = td_info.endpoint_no;
  873. if (td_info.direction == 2) {
  874. wk_table[2] |= USB_HOST_EP_IN;
  875. }
  876. wk_table[3] = USB_HOST_EP_INT;
  877. wk_table[4] = (uint8_t)td_info.msp;
  878. wk_table[5] = (uint8_t)(td_info.msp >> 8);
  879. cycle_time = chk_cycle(p_ed);
  880. p_g_ed->cycle_time = cycle_time;
  881. user_table->pipe_cycle = 0;
  882. while (cycle_time > 1) {
  883. cycle_time >>= 1;
  884. user_table->pipe_cycle++;
  885. }
  886. if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
  887. usbx_host_get_devadd(td_info.devadr, &devadd);
  888. if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) {
  889. user_table->pipe_cycle += 3;
  890. if (user_table->pipe_cycle > 7) {
  891. user_table->pipe_cycle = 7;
  892. }
  893. }
  894. }
  895. p_g_ed->pipe_no = user_table->pipe_number;
  896. usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
  897. set_togle(p_g_ed->pipe_no, p_td, p_ed);
  898. }
  899. static uint32_t chk_cycle(hced_t *p_ed) {
  900. uint32_t cnt;
  901. uint32_t hit_cnt = 0;
  902. uint32_t cycle_time = 1;
  903. hcca_t *p_hcca;
  904. hced_t *p_wk_ed;
  905. p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
  906. for (cnt = 0; cnt < 32; cnt++) {
  907. p_wk_ed = (hced_t *)p_hcca->IntTable[cnt];
  908. while (p_wk_ed != NULL) {
  909. if (p_wk_ed == p_ed) {
  910. hit_cnt++;
  911. break;
  912. }
  913. p_wk_ed = p_wk_ed->nextED;
  914. }
  915. }
  916. if (hit_cnt < 2) {
  917. cycle_time = 32;
  918. } else if (hit_cnt < 4) {
  919. cycle_time = 16;
  920. } else if (hit_cnt < 8) {
  921. cycle_time = 8;
  922. } else if (hit_cnt < 16) {
  923. cycle_time = 4;
  924. } else if (hit_cnt < 32) {
  925. cycle_time = 2;
  926. } else{
  927. cycle_time = 1;
  928. }
  929. return cycle_time;
  930. }
  931. static void int_trans(genelal_ed_t *p_g_ed) {
  932. hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
  933. tdinfo_t td_info;
  934. get_td_info(p_g_ed, &td_info);
  935. p_g_ed->trans_wait = 1;
  936. if (td_info.direction == 1) {
  937. usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
  938. } else {
  939. usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
  940. }
  941. }
  942. static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info) {
  943. hced_t *p_ed = p_g_ed->p_curr_ed;
  944. p_td_info->endpoint_no = (uint8_t)((p_ed->control >> 7) & 0x0000000F);
  945. p_td_info->msp = (p_ed->control >> 16) & 0x000007FF;
  946. p_td_info->devadr = p_ed->control & 0x0000000F;
  947. p_td_info->speed = (p_ed->control >> 13) & 0x00000001;
  948. p_td_info->direction = (p_ed->control >> 11) & 0x00000003;
  949. if ((p_ed->control & ED_FORMAT) == 0) {
  950. hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
  951. if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) {
  952. if ((p_td->control & TD_CTL_MSK_DP) == TD_SETUP) {
  953. p_td_info->direction = 0;
  954. } else if ((p_td->control & TD_CTL_MSK_DP) == TD_OUT) {
  955. p_td_info->direction = 1;
  956. } else {
  957. p_td_info->direction = 2;
  958. }
  959. }
  960. if (p_td->currBufPtr != NULL) {
  961. p_td_info->count = (uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1;
  962. } else {
  963. p_td_info->count = 0;
  964. }
  965. } else {
  966. #if (ISO_TRANS_MAX_NUM > 0)
  967. hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
  968. if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) {
  969. if ((p_isotd->control & TD_CTL_MSK_DP) == TD_SETUP) {
  970. p_td_info->direction = 0;
  971. } else if ((p_isotd->control & TD_CTL_MSK_DP) == TD_OUT) {
  972. p_td_info->direction = 1;
  973. } else {
  974. p_td_info->direction = 2;
  975. }
  976. }
  977. #endif
  978. }
  979. }
  980. static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed) {
  981. if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_0) {
  982. usbx_host_set_sqclr(pipe);
  983. } else if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_1) {
  984. usbx_host_set_sqset(pipe);
  985. } else if ((p_ed->headTD & ED_TOGLE_CARRY) == 0) {
  986. usbx_host_set_sqclr(pipe);
  987. } else {
  988. usbx_host_set_sqset(pipe);
  989. }
  990. }
  991. #if (ISO_TRANS_MAX_NUM > 0)
  992. static void iso_ed_task(void const * argument) {
  993. genelal_ed_t *p_iso_ed = &iso_ed[(uint32_t)argument];
  994. uint32_t wait_cnt = 0;
  995. uint32_t wait_time = 0;
  996. hcca_t *p_hcca;
  997. hced_t *p_ed;
  998. while (1) {
  999. (void)osSemaphoreWait(p_iso_ed->semid_list, osWaitForever);
  1000. if (p_iso_ed->p_curr_ed == NULL) {
  1001. p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
  1002. p_ed = (hced_t *)p_hcca->IntTable[0];
  1003. while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0)
  1004. && (p_iso_ed->p_curr_ed == NULL)) {
  1005. if (iso_trans_doing(p_ed, (uint32_t)argument) == 0) {
  1006. p_iso_ed->p_curr_ed = p_ed;
  1007. if (chk_iso_ed(p_iso_ed) != 0) {
  1008. iso_trans_setting(p_iso_ed, (uint32_t)argument);
  1009. } else {
  1010. p_iso_ed->p_curr_ed = NULL;
  1011. }
  1012. }
  1013. p_ed = p_ed->nextED;
  1014. }
  1015. p_iso_ed->psw_idx = 0;
  1016. }
  1017. if (p_iso_ed->p_curr_ed != NULL) {
  1018. while ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0) {
  1019. if (chk_iso_ed(p_iso_ed) != 0) {
  1020. wait_time = iso_chk_starting_frame(p_iso_ed);
  1021. if (wait_time != 0) {
  1022. osDelay(wait_time);
  1023. p_usb_reg->HcFmNumber += wait_time;
  1024. p_usb_reg->HcFmNumber &= 0x0000FFFF;
  1025. }
  1026. p_iso_ed->psw_idx = 0;
  1027. iso_trans(p_iso_ed);
  1028. (void)osSemaphoreWait(p_iso_ed->semid_wait, osWaitForever);
  1029. usbx_host_stop_transfer(p_iso_ed->pipe_no);
  1030. wait_cnt = 1;
  1031. } else {
  1032. if (wait_cnt > 0) {
  1033. wait_cnt--;
  1034. } else {
  1035. p_iso_ed->p_curr_ed = NULL;
  1036. }
  1037. break;
  1038. }
  1039. }
  1040. }
  1041. (void)osSemaphoreRelease(p_iso_ed->semid_list);
  1042. if (p_iso_ed->p_curr_ed == NULL) {
  1043. osDelay(10);
  1044. } else {
  1045. osDelay(1);
  1046. }
  1047. }
  1048. }
  1049. static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index) {
  1050. uint32_t cnt;
  1051. int32_t ret = 0;
  1052. for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
  1053. if ((index != cnt) && (iso_ed[cnt].p_curr_ed == p_ed)) {
  1054. ret = 1;
  1055. }
  1056. }
  1057. return ret;
  1058. }
  1059. static void chk_iso_td_done(genelal_ed_t *p_g_ed) {
  1060. hcca_t *p_hcca;
  1061. hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
  1062. uint32_t ConditionCode = RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
  1063. if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) {
  1064. p_g_ed->p_curr_ed->headTD = ((uint32_t)p_isotd->nextTD & 0xFFFFFFF0)
  1065. | (p_g_ed->p_curr_ed->headTD & 0x0000000F);
  1066. p_isotd->nextTD = (hcisotd_t *)p_usb_reg->HcDoneHead;
  1067. p_usb_reg->HcDoneHead = (uint32_t)p_g_ed->p_curr_td;
  1068. if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) {
  1069. p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
  1070. p_hcca->DoneHead = p_usb_reg->HcDoneHead;
  1071. p_usb_reg->HcDoneHead = 0x00000000;
  1072. p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
  1073. (void)osSemaphoreRelease(semid_cb);
  1074. }
  1075. }
  1076. }
  1077. static int32_t chk_iso_ed(genelal_ed_t *p_g_ed){
  1078. int32_t ret = 0;
  1079. hced_t *p_ed = p_g_ed->p_curr_ed;
  1080. if (((p_ed->control & ED_SKIP) != 0)
  1081. || ((p_ed->control & ED_FORMAT) == 0)
  1082. || ((p_ed->headTD & ED_HALTED) != 0)
  1083. || ((p_ed->tailTD & 0xFFFFFFF0) == (p_ed->headTD & 0xFFFFFFF0))) {
  1084. /* Do Nothing */
  1085. } else if ((p_ed->control & 0x0000007F) > 10) {
  1086. p_ed->headTD |= ED_HALTED;
  1087. } else {
  1088. p_g_ed->p_curr_td = (void *)(p_ed->headTD & 0xFFFFFFF0);
  1089. if (p_g_ed->p_curr_td == NULL) {
  1090. p_ed->headTD |= ED_HALTED;
  1091. } else {
  1092. hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
  1093. p_g_ed->p_start_buf = p_isotd->bufferPage0;
  1094. ret = 1;
  1095. }
  1096. }
  1097. return ret;
  1098. }
  1099. static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
  1100. tdinfo_t td_info;
  1101. USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_iso_ep_tbl1[index];
  1102. uint8_t wk_table[6];
  1103. uint16_t devadd;
  1104. get_td_info(p_g_ed, &td_info);
  1105. wk_table[0] = 0;
  1106. wk_table[1] = USB_HOST_ENDPOINT_DESC;
  1107. wk_table[2] = td_info.endpoint_no;
  1108. if (td_info.direction == 2) {
  1109. wk_table[2] |= USB_HOST_EP_IN;
  1110. }
  1111. wk_table[3] = USB_HOST_EP_ISO;
  1112. wk_table[4] = (uint8_t)td_info.msp;
  1113. wk_table[5] = (uint8_t)(td_info.msp >> 8);
  1114. p_g_ed->cycle_time = 1;
  1115. user_table->pipe_cycle = 0;
  1116. if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
  1117. usbx_host_get_devadd(td_info.devadr, &devadd);
  1118. if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) {
  1119. user_table->pipe_cycle += 3;
  1120. }
  1121. }
  1122. p_g_ed->pipe_no = user_table->pipe_number;
  1123. usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
  1124. }
  1125. static uint32_t iso_chk_starting_frame(genelal_ed_t *p_g_ed) {
  1126. hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
  1127. uint32_t starting_frame = p_isotd->control & 0x0000FFFF;
  1128. uint32_t wait_time = 0;
  1129. if ((p_g_ed->psw_idx == 0) && (starting_frame > p_usb_reg->HcFmNumber)) {
  1130. wait_time = starting_frame - p_usb_reg->HcFmNumber;
  1131. }
  1132. return wait_time;
  1133. }
  1134. static void iso_trans(genelal_ed_t *p_g_ed) {
  1135. hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
  1136. tdinfo_t td_info;
  1137. uint32_t buff_addr;
  1138. uint32_t data_size;
  1139. if (((uint32_t)p_isotd->offsetPSW[p_g_ed->psw_idx] & 0x00001000) == 0) {
  1140. buff_addr = (uint32_t)p_isotd->bufferPage0 & 0xFFFFF000;
  1141. } else {
  1142. buff_addr = (uint32_t)p_isotd->bufEnd & 0xFFFFF000;
  1143. }
  1144. buff_addr |= (uint32_t)p_isotd->offsetPSW[p_g_ed->psw_idx] & 0x00000FFF;
  1145. if (p_g_ed->psw_idx < RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_FC, TD_CTL_MSK_FC)) {
  1146. data_size = p_isotd->offsetPSW[p_g_ed->psw_idx + 1] - p_isotd->offsetPSW[p_g_ed->psw_idx];
  1147. } else {
  1148. data_size = (uint32_t)p_isotd->bufEnd - buff_addr + 1;
  1149. }
  1150. p_isotd->offsetPSW[p_g_ed->psw_idx] = (uint16_t)data_size;
  1151. get_td_info(p_g_ed, &td_info);
  1152. p_g_ed->trans_wait = 1;
  1153. if (td_info.direction == 1) {
  1154. usbx_host_start_send_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr);
  1155. } else {
  1156. usbx_host_start_receive_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr);
  1157. }
  1158. }
  1159. #endif
  1160. static void connect_check(void) {
  1161. uint32_t type = 0;
  1162. uint16_t stat;
  1163. uint16_t devadd = 0;
  1164. uint32_t wk_HcRhPortStatus1 = p_usb_reg->HcRhPortStatus1;
  1165. if (usbx_host_CheckAttach() == USB_HOST_ATTACH) {
  1166. type = 1;
  1167. }
  1168. if ((((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) == 0) && (type == 0))
  1169. || (((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) != 0) && (type != 0))) {
  1170. return;
  1171. }
  1172. if (type == 0) {
  1173. usbx_host_UsbDetach();
  1174. wk_HcRhPortStatus1 &= ~OR_RH_PORT_CCS;
  1175. } else {
  1176. usbx_host_UsbAttach();
  1177. stat = usbx_host_UsbBusReset();
  1178. RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB);
  1179. RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT);
  1180. if (stat == USB_HOST_HSMODE) {
  1181. wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA;
  1182. RZA_IO_RegWrite_16(&USB20X.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
  1183. g_usbx_host_UsbDeviceSpeed = USB_HOST_HIGH_SPEED;
  1184. } else if (stat == USB_HOST_FSMODE) {
  1185. wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA;
  1186. RZA_IO_RegWrite_16(&USB20X.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
  1187. g_usbx_host_UsbDeviceSpeed = USB_HOST_FULL_SPEED;
  1188. } else {
  1189. wk_HcRhPortStatus1 |= OR_RH_PORT_LSDA;
  1190. RZA_IO_RegWrite_16(&USB20X.SOFCFG, 1, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
  1191. g_usbx_host_UsbDeviceSpeed = USB_HOST_LOW_SPEED;
  1192. }
  1193. RZA_IO_RegWrite_16(&devadd, g_usbx_host_UsbDeviceSpeed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
  1194. usbx_host_init_pipe_status();
  1195. usbx_host_set_devadd(USB_HOST_DEVICE_0, &devadd);
  1196. wk_HcRhPortStatus1 |= OR_RH_PORT_CCS;
  1197. }
  1198. wk_HcRhPortStatus1 |= OR_RH_PORT_CSC;
  1199. p_usb_reg->HcRhPortStatus1 = wk_HcRhPortStatus1;
  1200. p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_RHSC;
  1201. (void)memset(&split_ctl, 0, sizeof(split_ctl));
  1202. }
  1203. void ohciwrapp_loc_Connect(uint32_t type) {
  1204. uint32_t cnt;
  1205. connect_change = type;
  1206. if (type == 0) {
  1207. if (ctl_ed.trans_wait == 1) {
  1208. ohciwrapp_loc_TransEnd(ctl_ed.pipe_no, TD_CC_DEVICENOTRESPONDING);
  1209. }
  1210. if (blk_ed.trans_wait == 1) {
  1211. ohciwrapp_loc_TransEnd(blk_ed.pipe_no, TD_CC_DEVICENOTRESPONDING);
  1212. }
  1213. for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) {
  1214. if (int_ed[cnt].trans_wait == 1) {
  1215. ohciwrapp_loc_TransEnd(int_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING);
  1216. }
  1217. }
  1218. #if (ISO_TRANS_MAX_NUM > 0)
  1219. for (cnt = 0; cnt< ISO_TRANS_MAX_NUM; cnt++) {
  1220. if (iso_ed[cnt].trans_wait == 1) {
  1221. hced_t *p_ed = iso_ed[cnt].p_curr_ed;
  1222. p_ed->headTD |= ED_HALTED;
  1223. ohciwrapp_loc_TransEnd(iso_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING);
  1224. }
  1225. }
  1226. #endif
  1227. }
  1228. (void)osSemaphoreRelease(semid_cb);
  1229. }
  1230. void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) {
  1231. uint32_t periodic = 0;
  1232. uint32_t cnt;
  1233. uint32_t sqmon;
  1234. hced_t *p_ed;
  1235. genelal_ed_t *p_wait_ed = NULL;
  1236. if (ctl_ed.pipe_no == pipe) {
  1237. p_wait_ed = &ctl_ed;
  1238. } else if (blk_ed.pipe_no == pipe) {
  1239. p_wait_ed = &blk_ed;
  1240. } else {
  1241. #if (ISO_TRANS_MAX_NUM > 0)
  1242. if (p_wait_ed == NULL) {
  1243. for (cnt = 0; cnt< ISO_TRANS_MAX_NUM; cnt++) {
  1244. if (iso_ed[cnt].pipe_no == pipe) {
  1245. p_wait_ed = &iso_ed[cnt];
  1246. break;
  1247. }
  1248. }
  1249. }
  1250. #endif
  1251. if (p_wait_ed == NULL) {
  1252. for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) {
  1253. if (int_ed[cnt].pipe_no == pipe) {
  1254. p_wait_ed = &int_ed[cnt];
  1255. periodic = 1;
  1256. break;
  1257. }
  1258. }
  1259. }
  1260. }
  1261. if (p_wait_ed == NULL) {
  1262. return;
  1263. }
  1264. p_ed = p_wait_ed->p_curr_ed;
  1265. if (p_ed == NULL) {
  1266. return;
  1267. }
  1268. if ((p_ed->control & ED_FORMAT) == 0) {
  1269. hctd_t *p_td = (hctd_t *)p_wait_ed->p_curr_td;
  1270. if (p_td != NULL) {
  1271. if (ConditionCode == TD_CC_NOERROR) {
  1272. /* ErrorCount */
  1273. RZA_IO_RegWrite_32(&p_td->control, 0, TD_CTL_SHFT_EC, TD_CTL_MSK_EC);
  1274. /* CurrentBufferPointer */
  1275. p_td->currBufPtr += ((uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1) - g_usbx_host_data_count[pipe];
  1276. } else {
  1277. /* ErrorCount */
  1278. RZA_IO_RegWrite_32(&p_td->control, 3, TD_CTL_SHFT_EC, TD_CTL_MSK_EC);
  1279. }
  1280. /* DataToggle */
  1281. sqmon = usbx_host_get_sqmon(pipe);
  1282. RZA_IO_RegWrite_32(&p_td->control, sqmon, TD_CTL_SHFT_T, TD_CTL_MSK_T);
  1283. if (sqmon == 0) {
  1284. p_ed->headTD &= ~ED_TOGLE_CARRY;
  1285. } else {
  1286. p_ed->headTD |= ED_TOGLE_CARRY;
  1287. }
  1288. /* ConditionCode */
  1289. RZA_IO_RegWrite_32(&p_td->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
  1290. if (p_wait_ed == &ctl_ed) {
  1291. chk_split_trans_setting(&ctl_ed);
  1292. }
  1293. chk_genelal_td_done(p_wait_ed);
  1294. if (periodic != 0) {
  1295. if (chk_genelal_ed(p_wait_ed) != 0) {
  1296. int_trans(p_wait_ed);
  1297. } else {
  1298. p_wait_ed->trans_wait = 0;
  1299. (void)osSemaphoreRelease(p_wait_ed->semid_wait);
  1300. }
  1301. } else {
  1302. p_wait_ed->trans_wait = 0;
  1303. (void)osSemaphoreRelease(p_wait_ed->semid_wait);
  1304. }
  1305. }
  1306. } else {
  1307. #if (ISO_TRANS_MAX_NUM > 0)
  1308. hcisotd_t *p_isotd = (hcisotd_t *)p_wait_ed->p_curr_td;
  1309. uint32_t next_trans = 0;
  1310. if (p_isotd != NULL) {
  1311. usbx_host_stop_transfer(pipe);
  1312. if (p_usb_reg->HcFmNumber < 0x0000FFFF) {
  1313. p_usb_reg->HcFmNumber++;
  1314. } else {
  1315. p_usb_reg->HcFmNumber = 0;
  1316. }
  1317. /* Size of packet */
  1318. p_isotd->offsetPSW[p_wait_ed->psw_idx] -= g_usbx_host_data_count[pipe];
  1319. /* ConditionCode */
  1320. RZA_IO_RegWrite_32(&p_isotd->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
  1321. RZA_IO_RegWrite_16(&p_isotd->offsetPSW[p_wait_ed->psw_idx],
  1322. (uint16_t)ConditionCode, TD_PSW_SHFT_CC, TD_PSW_MSK_CC);
  1323. if (usbx_host_CheckAttach() != USB_HOST_ATTACH) {
  1324. p_ed->headTD |= ED_HALTED;
  1325. }
  1326. if (p_wait_ed->psw_idx >= RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_FC, TD_CTL_MSK_FC)) {
  1327. p_wait_ed->psw_idx = 0;
  1328. chk_iso_td_done(p_wait_ed);
  1329. } else {
  1330. p_wait_ed->psw_idx++;
  1331. }
  1332. if (chk_iso_ed(p_wait_ed) != 0) {
  1333. if (iso_chk_starting_frame(p_wait_ed) == 0) {
  1334. iso_trans(p_wait_ed);
  1335. next_trans = 1;
  1336. }
  1337. }
  1338. if (next_trans == 0) {
  1339. p_wait_ed->trans_wait = 0;
  1340. (void)osSemaphoreRelease(p_wait_ed->semid_wait);
  1341. }
  1342. }
  1343. #endif
  1344. }
  1345. }