150 rivejä
6.1 KiB
C
150 rivejä
6.1 KiB
C
/**
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******************************************************************************
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* @file usb_regs.h
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* @author MCD Application Team
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* @version V2.1.0
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* @date 19-March-2012
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* @brief hardware registers
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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******************************************************************************
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*/
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#ifndef __USB_OTG_REGS_H__
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#define __USB_OTG_REGS_H__
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typedef struct //000h
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{
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__IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
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__IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
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__IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
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__IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
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__IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
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__IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
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__IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
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__IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
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__IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
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__IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
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__IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
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__IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
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uint32_t Reserved30[2]; /* Reserved 030h*/
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__IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
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__IO uint32_t CID; /* User ID Register 03Ch*/
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uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
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__IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
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__IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
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}
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USB_OTG_GREGS;
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typedef struct // 800h
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{
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__IO uint32_t DCFG; /* dev Configuration Register 800h*/
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__IO uint32_t DCTL; /* dev Control Register 804h*/
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__IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
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uint32_t Reserved0C; /* Reserved 80Ch*/
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__IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
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__IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
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__IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
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__IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
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uint32_t Reserved20; /* Reserved 820h*/
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uint32_t Reserved9; /* Reserved 824h*/
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__IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
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__IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
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__IO uint32_t DTHRCTL; /* dev thr 830h*/
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__IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
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}
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USB_OTG_DREGS;
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typedef struct
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{
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__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
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uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
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__IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
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uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
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__IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
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uint32_t Reserved14;
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__IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
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uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
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}
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USB_OTG_INEPREGS;
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typedef struct
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{
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__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
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uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
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__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
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uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
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__IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
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uint32_t Reserved14[3];
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}
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USB_OTG_OUTEPREGS;
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typedef struct
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{
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__IO uint32_t HCFG; /* Host Configuration Register 400h*/
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__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
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__IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
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uint32_t Reserved40C; /* Reserved 40Ch*/
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__IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
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__IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
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__IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
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}
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USB_OTG_HREGS;
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typedef struct
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{
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__IO uint32_t HCCHAR;
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__IO uint32_t HCSPLT;
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__IO uint32_t HCINT;
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__IO uint32_t HCINTMSK;
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__IO uint32_t HCTSIZ;
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uint32_t Reserved[3];
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}
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USB_OTG_HC_REGS;
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typedef struct
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{
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USB_OTG_GREGS GREGS;
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uint32_t RESERVED0[188];
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USB_OTG_HREGS HREGS;
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uint32_t RESERVED1[9];
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__IO uint32_t HPRT;
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uint32_t RESERVED2[47];
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USB_OTG_HC_REGS HC_REGS[8];
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uint32_t RESERVED3[128];
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USB_OTG_DREGS DREGS;
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uint32_t RESERVED4[50];
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USB_OTG_INEPREGS INEP_REGS[4];
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uint32_t RESERVED5[96];
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USB_OTG_OUTEPREGS OUTEP_REGS[4];
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uint32_t RESERVED6[160];
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__IO uint32_t PCGCCTL;
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uint32_t RESERVED7[127];
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__IO uint32_t FIFO[4][1024];
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}
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USB_OTG_CORE_REGS;
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#define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
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#define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
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#endif //__USB_OTG_REGS_H__
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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