1
0
This repo is archived. You can view files and clone it, but cannot push or open issues or pull requests.
tmk_keyboard_custom/converter/pc98_usb/config.h

127 lines
4.0 KiB
C
Raw Normal View History

2013-02-22 00:53:46 +00:00
/*
Copyright 2012 Jun Wako <wakojun@gmail.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef CONFIG_H
#define CONFIG_H
#define VENDOR_ID 0xFEED
2013-02-22 10:37:27 +00:00
#define PRODUCT_ID 0x9898
2013-02-22 00:53:46 +00:00
#define DEVICE_VER 0x0100
#define MANUFACTURER t.m.k.
#define PRODUCT PC98 keyboard converter
#define DESCRIPTION converts PC98 keyboard protocol into USB
/* matrix size */
2013-02-24 18:09:10 +00:00
#define MATRIX_ROWS 16
#define MATRIX_COLS 8
2013-02-22 00:53:46 +00:00
2013-02-24 09:10:50 +00:00
/* To use new keymap framework */
#define USE_KEYMAP_V2
2013-02-22 00:53:46 +00:00
/* key combination for command */
2013-02-24 18:09:10 +00:00
#define IS_COMMAND() ( \
2013-02-24 09:10:50 +00:00
host_get_first_key() == KC_CANCEL \
2013-02-22 00:53:46 +00:00
)
2013-02-22 10:37:27 +00:00
2013-02-24 09:10:50 +00:00
/* PC98 Reset Port shared with TXD */
2013-02-22 00:53:46 +00:00
#define PC98_RST_DDR DDRD
#define PC98_RST_PORT PORTD
2013-02-24 09:10:50 +00:00
#define PC98_RST_BIT 3
2013-02-22 10:37:27 +00:00
/* PC98 Ready Port */
2013-02-22 00:53:46 +00:00
#define PC98_RDY_DDR DDRD
#define PC98_RDY_PORT PORTD
#define PC98_RDY_BIT 4
2013-02-22 10:37:27 +00:00
/* PC98 Retry Port */
2013-02-22 00:53:46 +00:00
#define PC98_RTY_DDR DDRD
#define PC98_RTY_PORT PORTD
#define PC98_RTY_BIT 5
2013-02-24 18:09:10 +00:00
/*
* PC98 Serial(USART) configuration
* asynchronous, positive logic, 19200baud, bit order: LSB first
* 1-start bit, 8-data bit, odd parity, 1-stop bit
*/
/*
* Software Serial
*/
#define SERIAL_SOFT_BAUD 19200
#define SERIAL_SOFT_PARITY_ODD
#define SERIAL_SOFT_BIT_ORDER_LSB
#define SERIAL_SOFT_LOGIC_POSITIVE
2013-02-22 10:37:27 +00:00
/* RXD Port */
2013-02-24 18:09:10 +00:00
#define SERIAL_SOFT_RXD_DDR DDRD
#define SERIAL_SOFT_RXD_PORT PORTD
#define SERIAL_SOFT_RXD_PIN PIND
#define SERIAL_SOFT_RXD_BIT 2
2013-02-24 23:40:15 +00:00
#define SERIAL_SOFT_RXD_READ() (SERIAL_SOFT_RXD_PIN&(1<<SERIAL_SOFT_RXD_BIT))
2013-02-22 10:37:27 +00:00
/* RXD Interupt */
2013-02-24 18:09:10 +00:00
#define SERIAL_SOFT_RXD_VECT INT2_vect
#define SERIAL_SOFT_RXD_INIT() do { \
2013-02-22 00:53:46 +00:00
/* pin configuration: input with pull-up */ \
2013-02-24 18:09:10 +00:00
SERIAL_SOFT_RXD_DDR &= ~(1<<SERIAL_SOFT_RXD_BIT); \
SERIAL_SOFT_RXD_PORT |= (1<<SERIAL_SOFT_RXD_BIT); \
/* enable interrupt: INT2(falling edge) */ \
EICRA |= ((1<<ISC21)|(0<<ISC20)); \
EIMSK |= (1<<INT2); \
sei(); \
2013-02-22 00:53:46 +00:00
} while (0)
2013-02-24 18:09:10 +00:00
#define SERIAL_SOFT_RXD_INT_ENTER()
#define SERIAL_SOFT_RXD_INT_EXIT() do { \
/* clear interrupt flag */ \
EIFR = (1<<INTF2); \
2013-02-22 00:53:46 +00:00
} while (0)
2013-02-24 09:10:50 +00:00
/* TXD Port */
2013-02-24 18:09:10 +00:00
#define SERIAL_SOFT_TXD_DDR DDRD
#define SERIAL_SOFT_TXD_PORT PORTD
#define SERIAL_SOFT_TXD_PIN PIND
#define SERIAL_SOFT_TXD_BIT 3
2013-02-24 23:40:15 +00:00
#define SERIAL_SOFT_TXD_HI() do { SERIAL_SOFT_TXD_PORT |= (1<<SERIAL_SOFT_TXD_BIT); } while (0)
#define SERIAL_SOFT_TXD_LO() do { SERIAL_SOFT_TXD_PORT &= ~(1<<SERIAL_SOFT_TXD_BIT); } while (0)
2013-02-24 18:09:10 +00:00
#define SERIAL_SOFT_TXD_INIT() do { \
/* pin configuration: output */ \
SERIAL_SOFT_TXD_DDR |= (1<<SERIAL_SOFT_TXD_BIT); \
/* idle */ \
SERIAL_SOFT_TXD_ON(); \
2013-02-22 00:53:46 +00:00
} while (0)
2013-02-24 18:09:10 +00:00
/*
* Hardware Serial(UART)
*/
#ifdef __AVR_ATmega32U4__
#define SERIAL_UART_BAUD 19200
#define SERIAL_UART_DATA UDR1
#define SERIAL_UART_UBRR ((F_CPU/(16UL*SERIAL_UART_BAUD))-1)
#define SERIAL_UART_RXD_VECT USART1_RX_vect
#define SERIAL_UART_TXD_READY (UCSR1A&(1<<UDRE1))
#define SERIAL_UART_INIT() do { \
UBRR1L = (uint8_t) SERIAL_UART_UBRR; /* baud rate */ \
UBRR1H = (uint8_t) (SERIAL_UART_UBRR>>8); /* baud rate */ \
UCSR1B |= (1<<RXCIE1) | (1<<RXEN1); /* RX interrupt, RX: enable */ \
UCSR1B |= (0<<TXCIE1) | (1<<TXEN1); /* TX interrupt, TX: enable */ \
UCSR1C |= (1<<UPM11) | (1<<UPM10); /* parity: none(00), even(01), odd(11) */ \
sei(); \
} while(0)
#else
#error "USART configuration is needed."
#endif
2013-02-22 00:53:46 +00:00
#endif