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config.h 3.4KB

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  1. /*
  2. Copyright 2012 Jun Wako <[email protected]>
  3. This program is free software: you can redistribute it and/or modify
  4. it under the terms of the GNU General Public License as published by
  5. the Free Software Foundation, either version 2 of the License, or
  6. (at your option) any later version.
  7. This program is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. GNU General Public License for more details.
  11. You should have received a copy of the GNU General Public License
  12. along with this program. If not, see <http://www.gnu.org/licenses/>.
  13. */
  14. #ifndef CONFIG_H
  15. #define CONFIG_H
  16. #define VENDOR_ID 0xFEED
  17. #define PRODUCT_ID 0x9898
  18. #define DEVICE_VER 0x0100
  19. #define MANUFACTURER t.m.k.
  20. #define PRODUCT PC98 keyboard converter
  21. #define DESCRIPTION converts PC98 keyboard protocol into USB
  22. /* matrix size */
  23. #define MATRIX_ROWS 16
  24. #define MATRIX_COLS 8
  25. /* To use new keymap framework */
  26. #define USE_KEYMAP_V2
  27. /* key combination for command */
  28. #define IS_COMMAND() ( \
  29. host_get_first_key() == KC_CANCEL \
  30. )
  31. /* PC98 Serial(USART) configuration
  32. * asynchronous, positive logic, 19200baud, bit order: LSB first
  33. * 1-start bit, 8-data bit, odd parity, 1-stop bit
  34. */
  35. #define SERIAL_BAUD 19200
  36. #define SERIAL_PARITY_ODD
  37. #define SERIAL_BIT_ORDER_LSB
  38. #define SERIAL_LOGIC_POSITIVE
  39. /* PC98 Reset Port shared with TXD */
  40. #define PC98_RST_DDR DDRD
  41. #define PC98_RST_PORT PORTD
  42. #define PC98_RST_BIT 3
  43. /* PC98 Ready Port */
  44. #define PC98_RDY_DDR DDRD
  45. #define PC98_RDY_PORT PORTD
  46. #define PC98_RDY_BIT 4
  47. /* PC98 Retry Port */
  48. #define PC98_RTY_DDR DDRD
  49. #define PC98_RTY_PORT PORTD
  50. #define PC98_RTY_BIT 5
  51. /* RXD Port */
  52. #define SERIAL_RXD_DDR DDRD
  53. #define SERIAL_RXD_PORT PORTD
  54. #define SERIAL_RXD_PIN PIND
  55. #define SERIAL_RXD_BIT 2
  56. #ifdef SERIAL_LOGIC_NEGATIVE
  57. #define SERIAL_RXD_READ() ~(SERIAL_RXD_PIN&(1<<SERIAL_RXD_BIT))
  58. #else
  59. #define SERIAL_RXD_READ() (SERIAL_RXD_PIN&(1<<SERIAL_RXD_BIT))
  60. #endif
  61. /* RXD Interupt */
  62. #define SERIAL_RXD_VECT INT2_vect
  63. #define SERIAL_RXD_INIT() do { \
  64. /* pin configuration: input with pull-up */ \
  65. SERIAL_RXD_DDR &= ~(1<<SERIAL_RXD_BIT); \
  66. SERIAL_RXD_PORT |= (1<<SERIAL_RXD_BIT); \
  67. /* enable interrupt: INT2(falling edge) */ \
  68. EICRA |= ((1<<ISC21)|(0<<ISC20)); \
  69. EIMSK |= (1<<INT2); \
  70. sei(); \
  71. } while (0)
  72. #define SERIAL_RXD_INT_ENTER()
  73. #define SERIAL_RXD_INT_EXIT() do { \
  74. /* clear interrupt flag */ \
  75. EIFR = (1<<INTF2); \
  76. } while (0)
  77. /* TXD Port */
  78. #define SERIAL_TXD_DDR DDRD
  79. #define SERIAL_TXD_PORT PORTD
  80. #define SERIAL_TXD_PIN PIND
  81. #define SERIAL_TXD_BIT 3
  82. #ifdef SERIAL_LOGIC_NEGATIVE
  83. #define SERIAL_TXD_ON() do { SERIAL_TXD_PORT &= ~(1<<SERIAL_TXD_BIT); } while (0)
  84. #define SERIAL_TXD_OFF() do { SERIAL_TXD_PORT |= (1<<SERIAL_TXD_BIT); } while (0)
  85. #else
  86. #define SERIAL_TXD_ON() do { SERIAL_TXD_PORT |= (1<<SERIAL_TXD_BIT); } while (0)
  87. #define SERIAL_TXD_OFF() do { SERIAL_TXD_PORT &= ~(1<<SERIAL_TXD_BIT); } while (0)
  88. #endif
  89. #define SERIAL_TXD_INIT() do { \
  90. /* pin configuration: output */ \
  91. SERIAL_TXD_DDR |= (1<<SERIAL_TXD_BIT); \
  92. /* idle */ \
  93. SERIAL_TXD_ON(); \
  94. } while (0)
  95. #endif