output previous key state on TP1684 when scaning matrix.
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89feab2301
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@ -84,7 +84,7 @@ Two PCBs are connected by 15 lines. Vcc and GND use 3 lines each, other 9 lines
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2 Vcc(5V)
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2 Vcc(5V)
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3 Vcc(5V)
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3 Vcc(5V)
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4 TP1684 KEY: Low(0) when key pressed PE6 input(with pullup)
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4 TP1684 KEY: Low(0) when key pressed PE6 input(with pullup)
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5 TP1684 unknown:how to use PE7 input(with pullup)
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5 TP1684 KEY_PREV: assert previous key state??? PE7 output
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6 HC4051 A(bit0) select 8 rows(0 to 7) PB0 output
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6 HC4051 A(bit0) select 8 rows(0 to 7) PB0 output
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7 HC4051 B(bit1) PB1 output
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7 HC4051 B(bit1) PB1 output
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8 HC4051 C(bit2) PB2 output
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8 HC4051 C(bit2) PB2 output
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@ -148,9 +148,11 @@ Signals charts:
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(HHKB_chart1.jpg)
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(HHKB_chart1.jpg)
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Space bar locate at ROW:3 COL:7. Key are selected by HC4051(C,B,A) and LS145(C,B,A).
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Space bar locate at ROW:3 COL:7. A key is selected by HC4051(C,B,A) and LS145(C,B,A).
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Key state can be read on TP1684(4/KEY) while asserting low on LS145(D).
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Key state can be read on TP1684(4/KEY) while asserting low on LS145(D).
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Usage of TP1684(5) is unknown. Key state can be read without using this signal.
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Usage of TP1684(5) is not clear. Controller seemed to output previous key state on this line.
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However key state can be read without using this signal.
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(HHKB_chart2.jpg)
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(HHKB_chart2.jpg)
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@ -162,7 +164,13 @@ Matrix scan pseudo code:
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for (col: 0-7) {
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for (col: 0-7) {
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SELECT_COL(col); // set LS145(A,B,C)
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SELECT_COL(col); // set LS145(A,B,C)
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_delay_us(50);
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_delay_us(40);
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if (prev_key_state(row, col)) {
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KEY_PREV_ON;
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}
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_delay_us(7);
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ENALBLE_COL(); // set LS145(D) to low
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ENALBLE_COL(); // set LS145(D) to low
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@ -174,6 +182,7 @@ Matrix scan pseudo code:
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// not pressed
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// not pressed
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}
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}
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KEY_PREV_OFF;
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UNALBLE_COL(); // set LS145(D) to high
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UNALBLE_COL(); // set LS145(D) to high
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_delay_us(150);
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_delay_us(150);
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@ -19,13 +19,15 @@
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// PB3, PB4, PB5, PB6(A, B, C, D)
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// PB3, PB4, PB5, PB6(A, B, C, D)
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// use D as ENABLE: (enable: 0/unenable: 1)
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// use D as ENABLE: (enable: 0/unenable: 1)
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// key: KEY: (on: 0/ off:1)
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// key: KEY: (on: 0/ off:1)
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// UNKNOWN: unknown whether input or output
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// KEY_PREV: (on: 1/ off: 0)
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// PE6,PE7(KEY, UNKNOWN)
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// PE6,PE7(KEY, KEY_PREV)
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#define COL_ENABLE (1<<6)
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#define COL_ENABLE (1<<6)
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#define KEY_SELELCT(ROW, COL) (PORTB = COL_ENABLE|(((COL)&0x07)<<3)|((ROW)&0x07))
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#define KEY_SELELCT(ROW, COL) (PORTB = COL_ENABLE|(((COL)&0x07)<<3)|((ROW)&0x07))
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#define KEY_ENABLE (PORTB &= ~COL_ENABLE)
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#define KEY_ENABLE (PORTB &= ~COL_ENABLE)
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#define KEY_UNABLE (PORTB |= COL_ENABLE)
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#define KEY_UNABLE (PORTB |= COL_ENABLE)
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#define KEY_ON ((PINE&(1<<6)) ? false : true)
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#define KEY_STATE (PINE&(1<<6))
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#define KEY_PREV_ON (PORTE |= (1<<7))
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#define KEY_PREV_OFF (PORTE &= ~(1<<7))
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// matrix state buffer
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// matrix state buffer
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static uint8_t *matrix;
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static uint8_t *matrix;
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@ -52,9 +54,10 @@ void matrix_init(void)
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// row & col output(PB0-6)
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// row & col output(PB0-6)
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DDRB = 0xFF;
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DDRB = 0xFF;
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PORTB = KEY_SELELCT(0, 0);
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PORTB = KEY_SELELCT(0, 0);
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// KEY & VALID input with pullup(PE6,7)
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// KEY: input with pullup(PE6)
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DDRE = 0x3F;
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// KEY_PREV: output(PE7)
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PORTE = 0xC0;
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DDRE = 0xBF;
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PORTE = 0x40;
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// initialize matrix state: all keys off
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// initialize matrix state: all keys off
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for (int i=0; i < MATRIX_ROWS; i++) _matrix0[i] = 0x00;
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for (int i=0; i < MATRIX_ROWS; i++) _matrix0[i] = 0x00;
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@ -74,14 +77,19 @@ int matrix_scan(void)
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for (int row = 0; row < MATRIX_ROWS; row++) {
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for (int row = 0; row < MATRIX_ROWS; row++) {
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for (int col = 0; col < MATRIX_COLS; col++) {
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for (int col = 0; col < MATRIX_COLS; col++) {
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KEY_SELELCT(row, col);
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KEY_SELELCT(row, col);
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_delay_us(50); // from logic analyzer chart
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_delay_us(40); // from logic analyzer chart
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if (matrix_prev[row] & (1<<col)) {
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KEY_PREV_ON;
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}
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_delay_us(7); // from logic analyzer chart
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KEY_ENABLE;
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KEY_ENABLE;
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_delay_us(10); // from logic analyzer chart
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_delay_us(10); // from logic analyzer chart
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if (KEY_ON) {
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if (KEY_STATE) {
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matrix[row] |= (1<<col);
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} else {
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matrix[row] &= ~(1<<col);
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matrix[row] &= ~(1<<col);
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} else {
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matrix[row] |= (1<<col);
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}
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}
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KEY_PREV_OFF;
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KEY_UNABLE;
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KEY_UNABLE;
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_delay_us(150); // from logic analyzer chart
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_delay_us(150); // from logic analyzer chart
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}
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}
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