ChibiOS: prettify/document sleep_led code.
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@ -22,7 +22,7 @@ static const uint8_t breathing_table[64] = {
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15, 10, 6, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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15, 10, 6, 4, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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};
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};
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/* LP Timer interrupt handler */
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/* Low Power Timer interrupt handler */
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OSAL_IRQ_HANDLER(KINETIS_LPTMR0_IRQ_VECTOR) {
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OSAL_IRQ_HANDLER(KINETIS_LPTMR0_IRQ_VECTOR) {
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OSAL_IRQ_PROLOGUE();
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OSAL_IRQ_PROLOGUE();
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@ -63,7 +63,7 @@ OSAL_IRQ_HANDLER(KINETIS_LPTMR0_IRQ_VECTOR) {
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/* LPTMR clock options */
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/* LPTMR clock options */
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#define LPTMR_CLOCK_MCGIRCLK 0 /* 4MHz clock */
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#define LPTMR_CLOCK_MCGIRCLK 0 /* 4MHz clock */
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#define LPTMR_CLOCK_LPO 1 /* 1kHz clock */
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#define LPTMR_CLOCK_LPO 1 /* 1kHz clock */
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#define LPTMR_CLOCK_ERCLK32K 2
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#define LPTMR_CLOCK_ERCLK32K 2 /* external 32kHz crystal */
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#define LPTMR_CLOCK_OSCERCLK 3 /* output from OSC */
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#define LPTMR_CLOCK_OSCERCLK 3 /* output from OSC */
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/* Work around inconsistencies in Freescale naming */
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/* Work around inconsistencies in Freescale naming */
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@ -78,7 +78,8 @@ void sleep_led_init(void) {
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/* Reset LPTMR settings */
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/* Reset LPTMR settings */
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LPTMR0->CSR = 0;
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LPTMR0->CSR = 0;
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/* Set the compare value */
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/* Set the compare value */
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LPTMR0->CMR = 1; // trigger on counter value (i.e. every time)
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LPTMR0->CMR = 0; // trigger on counter value (i.e. every time)
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/* Set up clock source and prescaler */
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/* Set up clock source and prescaler */
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/* Software PWM
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/* Software PWM
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* ______ ______ __
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* ______ ______ __
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@ -90,28 +91,39 @@ void sleep_led_init(void) {
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* F periods/second[frequency]
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* F periods/second[frequency]
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* R * F interrupts/second
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* R * F interrupts/second
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*/
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*/
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/* === OPTION 1 === */
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/* === OPTION 1 === */
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// for 1kHz LPO
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#if 0
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// 1kHz LPO
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// No prescaler => 1024 irqs/sec
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// No prescaler => 1024 irqs/sec
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// LPTMR0->PSR = LPTMRx_PSR_PCS(LPTMR_CLOCK_LPO)|LPTMRx_PSR_PBYP;
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// Note: this is too slow for a smooth breathe
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LPTMR0->PSR = LPTMRx_PSR_PCS(LPTMR_CLOCK_LPO)|LPTMRx_PSR_PBYP;
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#endif /* OPTION 1 */
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/* === OPTION 2 === */
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/* === OPTION 2 === */
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// for nMHz IRC (n=4 on KL25Z, KL26Z and K20x; n=2 or 8 on KL27Z)
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#if 1
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// nMHz IRC (n=4 on KL25Z, KL26Z and K20x; n=2 or 8 on KL27Z)
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MCG->C2 |= MCG_C2_IRCS; // fast (4MHz) internal ref clock
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MCG->C2 |= MCG_C2_IRCS; // fast (4MHz) internal ref clock
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#if defined(KL27Z) // divide the 8MHz IRC by 2, to have the same MCGIRCLK speed as others
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#if defined(KL27) // divide the 8MHz IRC by 2, to have the same MCGIRCLK speed as others
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MCG->MC |= MCG_MC_LIRC_DIV2_DIV2;
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MCG->MC |= MCG_MC_LIRC_DIV2_DIV2;
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#endif /* KL27Z */
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#endif /* KL27 */
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MCG->C1 |= MCG_C1_IRCLKEN; // enable internal ref clock
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MCG->C1 |= MCG_C1_IRCLKEN; // enable internal ref clock
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// to work in stop mode, also MCG_C1_IREFSTEN
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// to work in stop mode, also MCG_C1_IREFSTEN
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// Divide 4MHz by 2^N (N=5) => 62500 irqs/sec =>
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// Divide 4MHz by 2^N (N=6) => 62500 irqs/sec =>
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// => approx F=61, R=256, duration = 4
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// => approx F=61, R=256, duration = 4
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LPTMR0->PSR = LPTMRx_PSR_PCS(LPTMR_CLOCK_MCGIRCLK)|LPTMRx_PSR_PRESCALE(5);
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LPTMR0->PSR = LPTMRx_PSR_PCS(LPTMR_CLOCK_MCGIRCLK)|LPTMRx_PSR_PRESCALE(6);
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#endif /* OPTION 2 */
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/* === OPTION 3 === */
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/* === OPTION 3 === */
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// for OSC output (external crystal), usually 8MHz or 16MHz
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#if 0
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// OSC0->CR |= OSC_CR_ERCLKEN; // enable ext ref clock
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// OSC output (external crystal), usually 8MHz or 16MHz
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OSC0->CR |= OSC_CR_ERCLKEN; // enable ext ref clock
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// to work in stop mode, also OSC_CR_EREFSTEN
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// to work in stop mode, also OSC_CR_EREFSTEN
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// Divide by 2^N
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// Divide by 2^N
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// LPTMR0->PSR = LPTMRx_PSR_PCS(LPTMR_CLOCK_OSCERCLK)|LPTMRx_PSR_PRESCALE(7);
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LPTMR0->PSR = LPTMRx_PSR_PCS(LPTMR_CLOCK_OSCERCLK)|LPTMRx_PSR_PRESCALE(7);
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#endif /* OPTION 3 */
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/* === END OPTIONS === */
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/* === END OPTIONS === */
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/* Interrupt on TCF set (compare flag) */
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/* Interrupt on TCF set (compare flag) */
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nvicEnableVector(LPTMR0_IRQn, 2); // vector, priority
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nvicEnableVector(LPTMR0_IRQn, 2); // vector, priority
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LPTMR0->CSR |= LPTMRx_CSR_TIE;
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LPTMR0->CSR |= LPTMRx_CSR_TIE;
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