@@ -46,26 +46,35 @@ message( "${CHIP}" ) | |||
set( MCU "${CHIP}" ) # For loading script compatibility | |||
#| Chip Size Database | |||
#| Chip Size and CPU Frequency Database | |||
#| Processor frequency. | |||
#| Normally the first thing your program should do is set the clock prescaler, | |||
#| so your program will run at the correct speed. You should also set this | |||
#| variable to same clock speed. The _delay_ms() macro uses this, and many | |||
#| examples use this variable to calculate timings. Do not add a "UL" here. | |||
#| MCHCK Based / Kiibohd-dfu | |||
if ( "${CHIP}" MATCHES "mk20dx128vlf5" ) | |||
set( SIZE_RAM 16384 ) | |||
set( SIZE_FLASH 126976 ) | |||
set( F_CPU "48000000" ) | |||
#| Kiibohd-dfu | |||
elseif ( "${CHIP}" MATCHES "mk20dx256vlh7" ) | |||
set( SIZE_RAM 65536 ) | |||
set( SIZE_FLASH 253952 ) | |||
set( F_CPU "72000000" ) | |||
#| Teensy 3.0 | |||
elseif ( "${CHIP}" MATCHES "mk20dx128" ) | |||
set( SIZE_RAM 16384 ) | |||
set( SIZE_FLASH 131072 ) | |||
set( F_CPU "48000000" ) | |||
#| Teensy 3.1 | |||
elseif ( "${CHIP}" MATCHES "mk20dx256" ) | |||
set( SIZE_RAM 65536 ) | |||
set( SIZE_FLASH 262144 ) | |||
set( F_CPU "48000000" ) # XXX Also supports 72 MHz, but may requires code changes | |||
#| Unknown ARM | |||
else () | |||
@@ -159,14 +168,6 @@ endif() | |||
set( OPT "s" ) | |||
#| Processor frequency. | |||
#| Normally the first thing your program should do is set the clock prescaler, | |||
#| so your program will run at the correct speed. You should also set this | |||
#| variable to same clock speed. The _delay_ms() macro uses this, and many | |||
#| examples use this variable to calculate timings. Do not add a "UL" here. | |||
set( F_CPU "48000000" ) | |||
#| Dependency Files | |||
#| Compiler flags to generate dependency files. | |||
set( GENDEPFLAGS "-MMD" ) |
@@ -63,6 +63,8 @@ static inline void delayMicroseconds(uint32_t usec) | |||
{ | |||
#if F_CPU == 96000000 | |||
uint32_t n = usec << 5; | |||
#elif F_CPU == 72000000 | |||
uint32_t n = usec << 5; // XXX Not accurate, assembly snippet needs to be updated | |||
#elif F_CPU == 48000000 | |||
uint32_t n = usec << 4; | |||
#elif F_CPU == 24000000 |
@@ -572,11 +572,21 @@ void ResetHandler() | |||
while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 2 ) ); | |||
// now we're in FBE mode | |||
#if F_CPU == 72000000 | |||
// config PLL input for 16 MHz Crystal / 8 = 2 MHz | |||
MCG_C5 = MCG_C5_PRDIV0( 7 ); | |||
#else | |||
// config PLL input for 16 MHz Crystal / 4 = 4 MHz | |||
MCG_C5 = MCG_C5_PRDIV0( 3 ); | |||
#endif | |||
#if F_CPU == 72000000 | |||
// config PLL for 72 MHz output (36 * 2 MHz Ext PLL) | |||
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0( 12 ); | |||
#else | |||
// config PLL for 96 MHz output | |||
MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0( 0 ); | |||
#endif | |||
// wait for PLL to start using xtal as its input | |||
while ( !(MCG_S & MCG_S_PLLST) ); | |||
@@ -588,6 +598,9 @@ void ResetHandler() | |||
#if F_CPU == 96000000 | |||
// config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash | |||
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 0 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 ); | |||
#elif F_CPU == 72000000 | |||
// config divisors: 72 MHz core, 36 MHz bus, 24 MHz flash | |||
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 0 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 2 ); | |||
#elif F_CPU == 48000000 | |||
// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash | |||
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 1 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 ); | |||
@@ -595,7 +608,7 @@ void ResetHandler() | |||
// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash | |||
SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 3 ) | SIM_CLKDIV1_OUTDIV2( 3 ) | SIM_CLKDIV1_OUTDIV4( 3 ); | |||
#else | |||
#error "Error, F_CPU must be 96000000, 48000000, or 24000000" | |||
#error "Error, F_CPU must be 96000000, 72000000, 48000000, or 24000000" | |||
#endif | |||
// switch to PLL as clock source, FLL input = 16 MHz / 512 | |||
MCG_C1 = MCG_C1_CLKS( 0 ) | MCG_C1_FRDIV( 4 ); | |||
@@ -604,8 +617,13 @@ void ResetHandler() | |||
while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 3 ) ); | |||
// now we're in PEE mode | |||
#if F_CPU == 72000000 | |||
// configure USB for 48 MHz clock | |||
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV( 2 ) | SIM_CLKDIV2_USBFRAC; // USB = 72 MHz PLL / 1.5 | |||
#else | |||
// configure USB for 48 MHz clock | |||
SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV( 1 ); // USB = 96 MHz PLL / 2 | |||
#endif | |||
// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0 | |||
SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL( 6 ); |
@@ -35,14 +35,17 @@ | |||
// ----- Defines ----- | |||
#if (F_CPU == 96000000) | |||
#define F_BUS 48000000 | |||
#define F_MEM 24000000 | |||
#define F_BUS 48000000 | |||
#define F_MEM 24000000 | |||
#elif (F_CPU == 72000000) | |||
#define F_BUS 36000000 | |||
#define F_MEM 24000000 | |||
#elif (F_CPU == 48000000) | |||
#define F_BUS 48000000 | |||
#define F_MEM 24000000 | |||
#define F_BUS 48000000 | |||
#define F_MEM 24000000 | |||
#elif (F_CPU == 24000000) | |||
#define F_BUS 24000000 | |||
#define F_MEM 24000000 | |||
#define F_BUS 24000000 | |||
#define F_MEM 24000000 | |||
#endif | |||