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while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 2 ) ); |
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while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 2 ) ); |
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// now we're in FBE mode |
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// now we're in FBE mode |
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#if F_CPU == 72000000 |
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// config PLL input for 16 MHz Crystal / 8 = 2 MHz |
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MCG_C5 = MCG_C5_PRDIV0( 7 ); |
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#else |
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// config PLL input for 16 MHz Crystal / 4 = 4 MHz |
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// config PLL input for 16 MHz Crystal / 4 = 4 MHz |
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MCG_C5 = MCG_C5_PRDIV0( 3 ); |
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MCG_C5 = MCG_C5_PRDIV0( 3 ); |
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#endif |
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#if F_CPU == 72000000 |
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// config PLL for 72 MHz output (36 * 2 MHz Ext PLL) |
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MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0( 12 ); |
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#else |
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// config PLL for 96 MHz output |
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// config PLL for 96 MHz output |
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MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0( 0 ); |
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MCG_C6 = MCG_C6_PLLS | MCG_C6_VDIV0( 0 ); |
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#endif |
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// wait for PLL to start using xtal as its input |
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// wait for PLL to start using xtal as its input |
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while ( !(MCG_S & MCG_S_PLLST) ); |
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while ( !(MCG_S & MCG_S_PLLST) ); |
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#if F_CPU == 96000000 |
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#if F_CPU == 96000000 |
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// config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash |
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// config divisors: 96 MHz core, 48 MHz bus, 24 MHz flash |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 0 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 ); |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 0 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 ); |
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#elif F_CPU == 72000000 |
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// config divisors: 72 MHz core, 36 MHz bus, 24 MHz flash |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 0 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 2 ); |
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#elif F_CPU == 48000000 |
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#elif F_CPU == 48000000 |
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// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash |
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// config divisors: 48 MHz core, 48 MHz bus, 24 MHz flash |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 1 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 ); |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 1 ) | SIM_CLKDIV1_OUTDIV2( 1 ) | SIM_CLKDIV1_OUTDIV4( 3 ); |
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// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash |
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// config divisors: 24 MHz core, 24 MHz bus, 24 MHz flash |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 3 ) | SIM_CLKDIV1_OUTDIV2( 3 ) | SIM_CLKDIV1_OUTDIV4( 3 ); |
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SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1( 3 ) | SIM_CLKDIV1_OUTDIV2( 3 ) | SIM_CLKDIV1_OUTDIV4( 3 ); |
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#else |
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#else |
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#error "Error, F_CPU must be 96000000, 48000000, or 24000000" |
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#error "Error, F_CPU must be 96000000, 72000000, 48000000, or 24000000" |
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#endif |
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#endif |
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// switch to PLL as clock source, FLL input = 16 MHz / 512 |
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// switch to PLL as clock source, FLL input = 16 MHz / 512 |
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MCG_C1 = MCG_C1_CLKS( 0 ) | MCG_C1_FRDIV( 4 ); |
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MCG_C1 = MCG_C1_CLKS( 0 ) | MCG_C1_FRDIV( 4 ); |
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while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 3 ) ); |
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while ( (MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST( 3 ) ); |
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// now we're in PEE mode |
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// now we're in PEE mode |
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#if F_CPU == 72000000 |
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// configure USB for 48 MHz clock |
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SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV( 2 ) | SIM_CLKDIV2_USBFRAC; // USB = 72 MHz PLL / 1.5 |
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#else |
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// configure USB for 48 MHz clock |
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// configure USB for 48 MHz clock |
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SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV( 1 ); // USB = 96 MHz PLL / 2 |
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SIM_CLKDIV2 = SIM_CLKDIV2_USBDIV( 1 ); // USB = 96 MHz PLL / 2 |
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#endif |
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// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0 |
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// USB uses PLL clock, trace is CPU clock, CLKOUT=OSCERCLK0 |
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SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL( 6 ); |
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SIM_SOPT2 = SIM_SOPT2_USBSRC | SIM_SOPT2_PLLFLLSEL | SIM_SOPT2_TRACECLKSEL | SIM_SOPT2_CLKOUTSEL( 6 ); |