d1e969ce8f
- Updated port switching pins (split USB and UART switching) - Added basic support for 2nd i2c bus - Updated key matrix - Fixed udev rules - Added missing register defines
390 行
9.6 KiB
C
390 行
9.6 KiB
C
/*
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* Copyright (C) 2014 Jan Rychter
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* Modifications (C) 2015-2016 Jacob Alexander
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files ( the "Software" ), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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// ----- Includes ----
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// Compiler Includes
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#include <Lib/ScanLib.h>
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// Project Includes
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#include <print.h>
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#include <kll_defs.h>
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// Local Includes
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#include "i2c.h"
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// ----- Variables -----
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volatile I2C_Channel i2c_channels[ISSI_I2C_Buses_define];
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uint32_t i2c_offset[] = {
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0x0, // Bus 0
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0x1000, // Bus 1
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};
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// ----- Functions -----
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inline void i2c_setup()
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{
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for ( uint8_t ch = 0; ch < ISSI_I2C_Buses_define; ch++ )
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{
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volatile uint8_t *I2C_F = (uint8_t*)(&I2C0_F) + i2c_offset[ch];
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volatile uint8_t *I2C_FLT = (uint8_t*)(&I2C0_FLT) + i2c_offset[ch];
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volatile uint8_t *I2C_C1 = (uint8_t*)(&I2C0_C1) + i2c_offset[ch];
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volatile uint8_t *I2C_C2 = (uint8_t*)(&I2C0_C2) + i2c_offset[ch];
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switch ( ch )
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{
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case 0:
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// Enable I2C internal clock
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SIM_SCGC4 |= SIM_SCGC4_I2C0; // Bus 0
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// External pull-up resistor
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PORTB_PCR0 = PORT_PCR_ODE | PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(2);
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PORTB_PCR1 = PORT_PCR_ODE | PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(2);
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break;
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case 1:
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// Enable I2C internal clock
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SIM_SCGC4 |= SIM_SCGC4_I2C1; // Bus 1
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// External pull-up resistor
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PORTC_PCR10 = PORT_PCR_ODE | PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(2);
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PORTC_PCR11 = PORT_PCR_ODE | PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(2);
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break;
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}
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// SCL Frequency Divider
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// 1.8 MBaud ( likely higher than spec )
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// 0x82 -> 36 MHz / (4 * 3) = 2.25 MBaud
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// 0x80 => mul(4)
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// 0x05 => ICL(5)
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*I2C_F = 0x84;
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*I2C_FLT = 4;
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*I2C_C1 = I2C_C1_IICEN;
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*I2C_C2 = I2C_C2_HDRS; // High drive select
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switch ( ch )
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{
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case 0:
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// Enable I2C Interrupt
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NVIC_ENABLE_IRQ( IRQ_I2C0 );
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break;
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case 1:
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// Enable I2C Interrupt
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NVIC_ENABLE_IRQ( IRQ_I2C1 );
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break;
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}
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}
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}
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uint8_t i2c_busy( uint8_t ch )
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{
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volatile I2C_Channel *channel = &( i2c_channels[ch] );
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if ( channel->status == I2C_BUSY )
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{
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return 1;
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}
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return 0;
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}
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uint8_t i2c_any_busy()
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{
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for ( uint8_t ch = 0; ch < ISSI_I2C_Buses_define; ch++ )
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{
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if ( i2c_busy( ch ) )
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return 1;
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}
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return 0;
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}
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// These are here for readability and correspond to bit 0 of the address byte.
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#define I2C_WRITING 0
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#define I2C_READING 1
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int32_t i2c_send_sequence(
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uint8_t ch,
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uint16_t *sequence,
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uint32_t sequence_length,
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uint8_t *received_data,
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void ( *callback_fn )( void* ),
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void *user_data
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) {
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volatile I2C_Channel *channel = &( i2c_channels[ch] );
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volatile uint8_t *I2C_C1 = (uint8_t*)(&I2C0_C1) + i2c_offset[ch];
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volatile uint8_t *I2C_S = (uint8_t*)(&I2C0_S) + i2c_offset[ch];
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volatile uint8_t *I2C_D = (uint8_t*)(&I2C0_D) + i2c_offset[ch];
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int32_t result = 0;
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uint8_t status;
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if ( channel->status == I2C_BUSY )
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{
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return -1;
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}
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// Debug
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/*
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for ( uint8_t c = 0; c < sequence_length; c++ )
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{
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printHex( sequence[c] );
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print(" ");
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}
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print(NL);
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*/
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channel->sequence = sequence;
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channel->sequence_end = sequence + sequence_length;
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channel->received_data = received_data;
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channel->status = I2C_BUSY;
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channel->txrx = I2C_WRITING;
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channel->callback_fn = callback_fn;
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channel->user_data = user_data;
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// reads_ahead does not need to be initialized
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// Acknowledge the interrupt request, just in case
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*I2C_S |= I2C_S_IICIF;
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*I2C_C1 = ( I2C_C1_IICEN | I2C_C1_IICIE );
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// Generate a start condition and prepare for transmitting.
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*I2C_C1 |= ( I2C_C1_MST | I2C_C1_TX );
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status = *I2C_S;
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if ( status & I2C_S_ARBL )
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{
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warn_print("Arbitration lost");
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result = -1;
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goto i2c_send_sequence_cleanup;
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}
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// Write the first (address) byte.
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*I2C_D = *channel->sequence++;
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// Everything is OK.
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return result;
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i2c_send_sequence_cleanup:
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*I2C_C1 &= ~( I2C_C1_IICIE | I2C_C1_MST | I2C_C1_TX );
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channel->status = I2C_ERROR;
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return result;
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}
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void i2c_isr( uint8_t ch )
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{
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volatile I2C_Channel* channel = &i2c_channels[ch];
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volatile uint8_t *I2C_C1 = (uint8_t*)(&I2C0_C1) + i2c_offset[ch];
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volatile uint8_t *I2C_S = (uint8_t*)(&I2C0_S) + i2c_offset[ch];
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volatile uint8_t *I2C_D = (uint8_t*)(&I2C0_D) + i2c_offset[ch];
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uint8_t element;
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uint8_t status;
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status = *I2C_S;
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// Acknowledge the interrupt request
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*I2C_S |= I2C_S_IICIF;
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// Arbitration problem
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if ( status & I2C_S_ARBL )
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{
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warn_msg("Arbitration error. Bus: ");
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printHex( ch );
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print(NL);
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*I2C_S |= I2C_S_ARBL;
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goto i2c_isr_error;
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}
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if ( channel->txrx == I2C_READING )
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{
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switch( channel->reads_ahead )
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{
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// All the reads in the sequence have been processed ( but note that the final data register read still needs to
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// be done below! Now, the next thing is either a restart or the end of a sequence. In any case, we need to
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// switch to TX mode, either to generate a repeated start condition, or to avoid triggering another I2C read
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// when reading the contents of the data register.
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case 0:
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*I2C_C1 |= I2C_C1_TX;
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// Perform the final data register read now that it's safe to do so.
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*channel->received_data++ = *I2C_D;
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// Do we have a repeated start?
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if ( ( channel->sequence < channel->sequence_end ) && ( *channel->sequence == I2C_RESTART ) )
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{
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// Generate a repeated start condition.
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*I2C_C1 |= I2C_C1_RSTA;
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// A restart is processed immediately, so we need to get a new element from our sequence. This is safe, because
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// a sequence cannot end with a RESTART: there has to be something after it. Note that the only thing that can
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// come after a restart is an address write.
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channel->txrx = I2C_WRITING;
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channel->sequence++;
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element = *channel->sequence;
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*I2C_D = element;
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}
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else
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{
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goto i2c_isr_stop;
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}
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break;
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case 1:
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// do not ACK the final read
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*I2C_C1 |= I2C_C1_TXAK;
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*channel->received_data++ = *I2C_D;
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break;
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default:
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*channel->received_data++ = *I2C_D;
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break;
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}
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channel->reads_ahead--;
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}
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// channel->txrx == I2C_WRITING
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else
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{
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// First, check if we are at the end of a sequence.
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if ( channel->sequence == channel->sequence_end )
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goto i2c_isr_stop;
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// We received a NACK. Generate a STOP condition and abort.
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if ( status & I2C_S_RXAK )
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{
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warn_print("NACK Received");
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goto i2c_isr_error;
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}
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// check next thing in our sequence
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element = *channel->sequence;
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// Do we have a restart? If so, generate repeated start and make sure TX is on.
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if ( element == I2C_RESTART )
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{
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*I2C_C1 |= I2C_C1_RSTA | I2C_C1_TX;
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// A restart is processed immediately, so we need to get a new element from our sequence.
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// This is safe, because a sequence cannot end with a RESTART: there has to be something after it.
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channel->sequence++;
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element = *channel->sequence;
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// Note that the only thing that can come after a restart is a write.
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*I2C_D = element;
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}
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else
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{
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if ( element == I2C_READ ) {
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channel->txrx = I2C_READING;
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// How many reads do we have ahead of us ( not including this one )?
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// For reads we need to know the segment length to correctly plan NACK transmissions.
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// We already know about one read
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channel->reads_ahead = 1;
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while (
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( ( channel->sequence + channel->reads_ahead ) < channel->sequence_end ) &&
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( *( channel->sequence + channel->reads_ahead ) == I2C_READ )
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) {
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channel->reads_ahead++;
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}
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// Switch to RX mode.
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*I2C_C1 &= ~I2C_C1_TX;
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// do not ACK the final read
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if ( channel->reads_ahead == 1 )
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{
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*I2C_C1 |= I2C_C1_TXAK;
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}
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// ACK all but the final read
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else
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{
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*I2C_C1 &= ~( I2C_C1_TXAK );
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}
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// Dummy read comes first, note that this is not valid data!
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// This only triggers a read, actual data will come in the next interrupt call and overwrite this.
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// This is why we do not increment the received_data pointer.
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*channel->received_data = *I2C_D;
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channel->reads_ahead--;
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}
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// Not a restart, not a read, must be a write.
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else
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{
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*I2C_D = element;
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}
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}
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}
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channel->sequence++;
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return;
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i2c_isr_stop:
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// Generate STOP ( set MST=0 ), switch to RX mode, and disable further interrupts.
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*I2C_C1 &= ~( I2C_C1_MST | I2C_C1_IICIE | I2C_C1_TXAK );
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channel->status = I2C_AVAILABLE;
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// Call the user-supplied callback function upon successful completion (if it exists).
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if ( channel->callback_fn )
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{
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// Delay 10 microseconds before starting linked function
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// TODO, is this chip dependent? -HaaTa
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delayMicroseconds(10);
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( *channel->callback_fn )( channel->user_data );
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}
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return;
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i2c_isr_error:
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// Generate STOP and disable further interrupts.
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*I2C_C1 &= ~( I2C_C1_MST | I2C_C1_IICIE );
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channel->status = I2C_ERROR;
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return;
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}
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void i2c0_isr()
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{
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i2c_isr( 0 );
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}
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void i2c1_isr()
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{
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i2c_isr( 1 );
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}
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